Patents by Inventor Dong-chun Lee

Dong-chun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070181993
    Abstract: A printed circuit board (PCB) may include a substrate. A copper layer may be formed over a portion of the substrate, the copper layer including at least one of a metallic powder and a ceramic powder.
    Type: Application
    Filed: January 30, 2007
    Publication date: August 9, 2007
    Inventors: Jae-Hoon Choi, Kwang-Su Yu, Hyo-Jae Bang, Dong-Chun Lee
  • Publication number: 20070172690
    Abstract: A joining method, a method of mounting a semiconductor package (PKG) using the same, and a substrate-joining structure prepared thereby are provided. The joining method may comprise placing a first junction composition including tin and silver, and a second junction composition, including tin and bismuth to contact each other and forming a junction by performing a thermal treatment on the junction compositions at a temperature of at least 170° C. or higher.
    Type: Application
    Filed: April 7, 2006
    Publication date: July 26, 2007
    Inventors: Si-suk Kim, Kwang-su Yu, Dong-chun Lee, Jae-hoon Choi
  • Publication number: 20070161224
    Abstract: In one embodiment, a semiconductor module includes at least one semiconductor chip package, a board having functional pads and dummy pads, and at least one solder joint electrically connecting the semiconductor chip package and one of the functional pads of the board. Furthermore, at least one supporting solder bump is formed on one of the dummy pads and disposed under a portion of the semiconductor chip package. For example, the supporting solder bump may be disposed under a peripheral area of the semiconductor chip package.
    Type: Application
    Filed: March 16, 2007
    Publication date: July 12, 2007
    Inventors: Chang-Yong Park, Byung-Man Kim, Dong-Chun Lee, Yong-Hyun Kim, Kwang-Seop Kim, Dong-Woo Shin, Kwang-Ho Chun
  • Publication number: 20070120220
    Abstract: In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 31, 2007
    Inventors: Jung-Taek Lim, Dong-Chun Lee, Young-Jee Yoon, Sung-Hong Park
  • Publication number: 20070109758
    Abstract: Example embodiments may be directed to a printed circuit board having an insulating substrate, pads disposed on the surface of the insulating substrate, a solder resist, and a solder moving portion. Leads of a semiconductor package may be mounted on the insulating substrate. The pads to which the leads of the semiconductor package are connected may be disposed on the surface of the insulating substrate. The solder resist layer may cover the insulating substrate, but may also contain openings exposing at least a portion of the pads to which the leads of the semiconductor package are connected. During the process by which each semiconductor lead is connected to a pad, the solder moving portion on the pad may allow an adhesion solder coating each of the leads of the semiconductor package to move towards a shoulder portion of the semiconductor package leads.
    Type: Application
    Filed: November 14, 2006
    Publication date: May 17, 2007
    Inventors: Seong-Chan Han, Dong-Chun Lee, Kwang-Su Yu, Dong-Woo Shin, Hyo-Jae Bang, Hyun-Seok Choi, Si-Suk Kim
  • Patent number: 7215026
    Abstract: In one embodiment, a semiconductor module includes at least one semiconductor chip package, a board having functional pads and dummy pads, and at least one solder joint electrically connecting the semiconductor chip package and one of the functional pads of the board. Furthermore, at least one supporting solder bump is formed on one of the dummy pads and disposed under a portion of the semiconductor chip package. For example, the supporting solder bump may be disposed under a peripheral area of the semiconductor chip package.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: May 8, 2007
    Assignee: Samsung Electonics Co., Ltd
    Inventors: Chang-Yong Park, Byung-Man Kim, Dong-Chun Lee, Yong-Hyun Kim, Kwang-Seop Kim, Dong-Woo Shin, Kwang-Ho Chun
  • Publication number: 20070069378
    Abstract: In one embodiment, a semiconductor module includes at least one semiconductor chip package, a board having functional pads and dummy pads, and at least one solder joint electrically connecting the semiconductor chip package and one of the functional pads of the board. Furthermore, at least one supporting solder bump is formed on one of the dummy pads and disposed under a portion of the semiconductor chip package. For example, the supporting solder bump may be disposed under a peripheral area of the semiconductor chip package.
    Type: Application
    Filed: November 28, 2006
    Publication date: March 29, 2007
    Inventors: Chang-Yong Park, Byung-Man Kim, Dong-Chun Lee, Yong-Hyun Kim, Kwang-Seop Kim, Dong-Woo Shin, Kwang-Ho Chun
  • Publication number: 20070072467
    Abstract: A method of testing a substrate may involve photographing a first chip on a first face of the substrate to obtain a first image of the first chip, and photographing a second chip on a second face of the substrate opposite to the first face without reversing the substrate to obtain a second image of the second chip. The normality of the first and the second chips may be determined based on the first and the second images.
    Type: Application
    Filed: September 25, 2006
    Publication date: March 29, 2007
    Inventors: Young-Soo Lee, Dong-Chun Lee, Seong-Chan Han, Hyo-Jae Bang
  • Publication number: 20070047377
    Abstract: Example embodiments of the present invention may include a printed circuit board, a method of manufacturing the printed circuit board, and a memory module/socket assembly. Example embodiments of the present invention may increase the number of contact taps on a memory module, in addition, a force required to insert the memory module into a module socket may be decreased.
    Type: Application
    Filed: August 9, 2006
    Publication date: March 1, 2007
    Inventors: Hyo-Jae Bang, Dong-Chun Lee, Ho-Geon Song, Seong-Chan Han, Kwang-Su Yu, Dong-Woo Shin
  • Publication number: 20070013901
    Abstract: An optical inspection tool used to detect surface defects of a substrate include a chuck for holding a substrate and a lens unit disposed over the chuck. The lens unit includes at least a pair of oblique beam paths therein, wherein light penetrating the beam paths travels without angular deflection. The beam paths take the form of spaces formed through the lens unit, or flat portions formed on a lens within the lens unit. A camera is installed on the lens unit, and the camera converts light passing through the lens unit into an image. Methods of detecting surface defects of the substrate using the inspection tool are also provided.
    Type: Application
    Filed: June 12, 2006
    Publication date: January 18, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-An Kim, Dong-Chun Lee, Chung-Sam Jun, Ik-Chul Kim, Sang-Hee Kim
  • Publication number: 20070008703
    Abstract: A heat spreader includes a heat sinking plate and a pressure clip. The heat sinking plate radiates the heat away from a heat source. The pressure clip fixes the heat sinking plate to the heat source. The pressure clip includes a spine (pressing part), one or more ribs and hook parts. The spine is arranged on the heat sinking plate. The one or more ribs extend from the spine and contact the heat source. The hook parts extend from the spine and are supported by the heat source. The pressure clip further includes mounting parts that couple the spine to the hook parts. A bending space is formed between the spine and the heat sinking plate. The heat spreader may be attached to a printed circuit board (PCB) with, e.g., a one-touch method, so that assembling processes of the memory module may be automated.
    Type: Application
    Filed: July 6, 2006
    Publication date: January 11, 2007
    Inventors: Chang-Yong Park, Hyun-Jong Oh, Yong-Hyun Kim, Dong-Woo Shin, Kyung-Du Kim, Dong-Chun Lee, Kwang-Ho Chun
  • Publication number: 20060283009
    Abstract: An electronic component mounting apparatus that includes a demagnetizer used to demagnetize a head nozzle, and a method for demagnetizing an electronic component apparatus. The method may include setting conditions, mounting electronic components, and demagnetizing a head nozzle of the electronic component mounting apparatus based on the conditions.
    Type: Application
    Filed: June 15, 2006
    Publication date: December 21, 2006
    Inventors: Dong-Woo Shin, Byong-Kun Bae, Nam-Yong Oh, Dong-Chun Lee, Seong-Chan Han, Sun-Kyu Hwang
  • Publication number: 20060231949
    Abstract: In one embodiment, a semiconductor module includes at least one semiconductor chip package, a board having functional pads and dummy pads, and at least one solder joint electrically connecting the semiconductor chip package and one of the functional pads of the board. Furthermore, at least one supporting solder bump is formed on one of the dummy pads and disposed under a portion of the semiconductor chip package. For example, the supporting solder bump may be disposed under a peripheral area of the semiconductor chip package.
    Type: Application
    Filed: October 11, 2005
    Publication date: October 19, 2006
    Inventors: Chang-Yong Park, Byung-Man Kim, Dong-Chun Lee, Yong-Hyun Kim, Kwang-Seop Kim, Dong-Woo Shin, Kwang-Ho Chun
  • Patent number: 7061768
    Abstract: An open socket, into which a module can be inserted, may include: a body into which the module is insertable; a pin to contact an electrical connection member of the inserted module, the pin serving as at least a part of an electrical signal path to/from the module upon insertion thereof; an elastic biasing member to exert an elastic biasing force to cause the pin to contact the module; and at least one lower support to limit insertion depth as being a depth at which a lower portion of the inserted module comes to rest upon the at least one lower support; the body and the at least one lower support being constructed and arranged to provide a gap adjacent the at least one support, which leaves an area of the socket underlying the lower portion of the inserted module open to the outside.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: June 13, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Chun Lee, Byung-Man Kim, Kwang-Su Yu, Dong-Woo Shin, Young-Soo Lee
  • Publication number: 20060102997
    Abstract: A semiconductor module and a method of manufacturing a semiconductor module including at least one chip package, at least one module board, at least one conductive element provided between the first chip package and the module board and a protector for applying pressure to the conductive element, the module board, and the first chip package and/or acting as a heat sink for the first chip package.
    Type: Application
    Filed: September 23, 2005
    Publication date: May 18, 2006
    Inventors: Hyo-Jae Bang, Byung-Man Kim, Dong-Chun Lee, Kwang-Su Yu
  • Patent number: 7027638
    Abstract: A method for correcting color variations on the surface of a wafer, a method for selectively detecting a defect from different patterns, and computer readable recording media for the same are provided. Color variations in images of different parts of a wafer can be corrected using the mean and standard deviation of grey level values for the pixels forming each of the different parts of the wafer. In addition, different threshold values are applied to metal interconnect patterns and spaces of the wafer so that a defect can be selectively detected from the different patterns. Thus, a bridge known as a fatal, or killing defect to a semiconductor device can be detected without also falsely detecting grains as fatal defects. Due to increased defect screening capacity of the methods, the defect detecting method can be further efficiently managed.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: April 11, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chung-sam Jun, Sang-mun Chon, Hyoung-jin Kim, Dong-chun Lee, Sang-bong Choi, Sung-gon Ryu
  • Publication number: 20060043578
    Abstract: A semiconductor device, which may include a heat sink using a thermal induced adhesive is provided. The adhesive strength of the thermal induced adhesive at room temperature may be reduced when heated. The thermal induced adhesive may attach the heat sink to the semiconductor device, and may result in a thinner semiconductor device.
    Type: Application
    Filed: January 21, 2005
    Publication date: March 2, 2006
    Inventors: Hyo-Jae Bang, Byung-Man Kim, Dong-Chun Lee, Kwang-Su Yu
  • Publication number: 20060029286
    Abstract: An image processing method is disclosed. The method comprises capturing a plurality of images of a sample using a scanning electron microscope (SEM). The method further comprising computing a mean value for each pixel location in the plurality of images and forming an integrated image with the mean values. The method further comprises filtering the integrated image using a median filter.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 9, 2006
    Inventors: Jung-Taek Lim, Hyo-Cheon Kang, Chung-Sam Jun, Dong-Chun Lee, Byoung-Ho Lee
  • Publication number: 20050118878
    Abstract: An open socket, into which a module can be inserted, may include: a body into which the module is insertable; a pin to contact an electrical connection member of the inserted module, the pin serving as at least a part of an electrical signal path to/from the module upon insertion thereof; an elastic biasing member to exert an elastic biasing force to cause the pin to contact the module; and at least one lower support to limit insertion depth as being a depth at which a lower portion of the inserted module comes to rest upon the at least one lower support; the body and the at least one lower support being constructed and arranged to provide a gap adjacent the at least one support, which leaves an area of the socket underlying the lower portion of the inserted module open to the outside.
    Type: Application
    Filed: June 17, 2004
    Publication date: June 2, 2005
    Inventors: Dong-Chun Lee, Byung-Man Kim, Kwang-Su Yu, Dong-Woo Shin, Young-Soo Lee
  • Publication number: 20050000635
    Abstract: A method and arrangement for attaching labels to a plurality of semiconductor modules arranged on a double-sided substrate is described which may shorten a process stream in an effort to reduce equipment costs. An exemplary arrangement may include at least one label attaching unit configured to attach labels to a plurality of semiconductor modules mounted on one of a first surface and a second surface of the double-sided substrate, and may include at least one turner configured to turn over the double-sided substrate to expose one of the first surface and second surface to the label attaching unit.
    Type: Application
    Filed: July 2, 2004
    Publication date: January 6, 2005
    Inventors: Young-Soo Lee, Myung-Jong Eom, Byung-Man Kim, Dong-Chun Lee