Patents by Inventor Dong-soo Lee

Dong-soo Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220130065
    Abstract: Disclosed is a method for analyzing a thickness of a cortical region, performed by a computing device. The method may include: extracting a plurality of interfaces included in a cortical region based on a mask generated from a medical image including at least one brain region; and estimating a thickness of the cortical region based on the plurality of interfaces.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 28, 2022
    Inventors: Eunpyeong HONG, Wonmo JUNG, Sejin PARK, Hyunwoo OH, Dong Soo LEE, Weon Jin KIM, Jinkyeong SUNG
  • Publication number: 20220059533
    Abstract: A semiconductor device includes first and second active patterns disposed on a substrate, a field insulating film disposed between the first and second active patterns, a first gate structure intersecting the first active pattern, and a second gate structure intersecting the second active pattern, in which the first gate structure includes a first gate insulating film on the first active pattern, a first upper insertion film on the first gate insulating film, and a first upper conductive film on the first upper insertion film, and the second gate structure includes a second gate insulating film on the second active pattern, a second upper insertion film on the second gate insulating film, and a second upper conductive film on the second upper insertion film. Each of the first and second upper insertion films may include an aluminum nitride film. Each of the first and second upper conductive films may include aluminum.
    Type: Application
    Filed: March 31, 2021
    Publication date: February 24, 2022
    Inventors: SU YOUNG BAE, Jong Ho Park, Dong Soo Lee, Wan Don Kim
  • Publication number: 20220026485
    Abstract: A test handler includes a pusher which includes a pusher end which comes into contact with a DUT (Device Under Test) to transfer heat, and a pusher body which conducts heat to the pusher end, the pusher end separating a test tray for fixing the DUT and the pusher body from each other; a porous match plate including a pusher arrangement region in which the pusher body is placed, and a plurality of holes placed adjacent to the pusher arrangement region; a heater placed on an upper surface of the porous match plate to control temperature of the pusher; and an airflow input port placed on the heater to provide the airflow to the plurality of holes, in which the airflow passes through the plurality of holes and passes through a separated space between the test tray and the pusher body.
    Type: Application
    Filed: March 24, 2021
    Publication date: January 27, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yeong Seok KIM, Suk Byung CHAE, Dong Soo LEE, Sang Ho JANG
  • Publication number: 20210311630
    Abstract: Provided is a module mounted in a server to share a block-level storage and resources. The module includes: a HBA card unit for connection to an external server; an internal disk unit providing a storage space inside a server; a setting unit allocating the storage space of the internal disk unit; a target driver unit implementing a SCSI protocol, communicating with the external server and setting volumes to a storage mode or a server mode; and a target core unit routing data of the internal disk unit and the target driver unit depending on the storage mode or the server mode. The storage mode allows the volumes to be used as a storage of the external server. The server mode allows the volumes to be used as a storage inside the server. The target driver unit can switch the volumes from the server mode to the storage mode.
    Type: Application
    Filed: October 30, 2020
    Publication date: October 7, 2021
    Inventors: Dong Soo LEE, Won Hun KIM
  • Publication number: 20210288005
    Abstract: A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.
    Type: Application
    Filed: February 19, 2021
    Publication date: September 16, 2021
    Applicant: Nepes CO., LTD.
    Inventors: Hyun Sik KIM, Seung Hwan SHIN, Yong Tae KWON, Dong Hoon SEO, Hee Cheol KIM, Dong Soo LEE
  • Patent number: 11101695
    Abstract: An electronic device is provided. The electronic device includes a receiving circuit configured to wirelessly receive power and output AC power, a rectifying circuit configured to rectify the AC power from the receiving circuit, wherein the rectifying circuit may include a first P-MOSFET configured to transfer a positive amplitude of power to an output terminal of the rectifying circuit while the AC power has the positive amplitude and to prevent transferring a negative amplitude of power to the output terminal of the rectifying circuit while the AC power has the negative amplitude, and a forward loss compensating circuit connected with the first P-MOSFET configured to reduce a threshold voltage of the first P-MOSFET while the AC power has the positive amplitude.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: August 24, 2021
    Assignees: Samsung Electronics Co., Ltd., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Sung-Ku Yeo, Sang-Yun Kim, Jae-Seok Park, Young-Ho Ryu, Kang-Yoon Lee, Hamed Abbasizadeh, Sang-Wook Kwon, Thi Kim Nga Truong, Dong-In Kim, Sung-Bum Park, Dong-Soo Lee, Seung Il Huh
  • Publication number: 20210208535
    Abstract: Provided are a system and method for digital holographic imaging which are not affected by external vibrations. The system for digital holographic imaging includes a light source and optical system section configured to split generated beams and including a sample through which the beams pass, a lens, and a grating disposed behind the lens; an object signal acquisition section configured to receive the split beams and acquire an interference signal; and an image processor configured to acquire a three-dimensional (3D) image of an object by using the acquired interference signal.
    Type: Application
    Filed: March 20, 2020
    Publication date: July 8, 2021
    Inventors: Gi Hyeon MIN, Keo Sik KIM, Hyun Seo KANG, Kye Eun KIM, Sung Chang KIM, Ji Hyoung RYU, Si Woong PARK, Hyoung Jun PARK, Dong Hoon SON, Chan Il YEO, Dong Soo LEE, Byung Tak LEE, Young Soon HEO
  • Publication number: 20210151610
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Jae-Jung KIM, Dong-Soo LEE, Sang-Yong KIM, Jin-Kyu JANG, Won-Keun CHUNG, Sang-Jin HYUN
  • Patent number: 10947949
    Abstract: A self-diagnosis method for an ignition coil includes receiving and confirming a current flag (C/F) signal through monitoring of primary current of an ignition coil; monitoring secondary current of the ignition coil upon receiving the C/F signal and confirming whether a fault flag (F/F) signal for determining whether misfire of the ignition coil occurs is input; and determining whether an abnormal signal of the ignition coil is generated based on the result of confirming the C/F signal and the F/F signal respectively.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: March 16, 2021
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Dong-Soo Lee, Jung-Hun Lee, Sung-Kwan Bae, Do-Geun Jung
  • Patent number: 10923602
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Jung Kim, Dong-Soo Lee, Sang-Yong Kim, Jin-Kyu Jang, Won-Keun Chung, Sang-Jin Hyun
  • Publication number: 20200300209
    Abstract: A self-diagnosis method for an ignition coil includes receiving and confirming a current flag (C/F) signal through monitoring of primary current of an ignition coil; monitoring secondary current of the ignition coil upon receiving the C/F signal and confirming whether a fault flag (F/F) signal for determining whether misfire of the ignition coil occurs is input; and determining whether an abnormal signal of the ignition coil is generated based on the result of confirming the C/F signal and the F/F signal respectively.
    Type: Application
    Filed: November 18, 2019
    Publication date: September 24, 2020
    Inventors: Dong-Soo Lee, Jung-Hun Lee, Sung-Kwan Bae, Do-Geun Jung
  • Patent number: 10559687
    Abstract: A semiconductor device including a substrate; a first and second active region on the substrate; a first recess intersecting with the first active region; a second recess intersecting with the second active region; a gate spacer extending along sidewalls of the first and second recess; a first lower high-k dielectric film in the first recess and including a first high-k dielectric material in a first concentration and a second high-k dielectric material; a second lower high-k dielectric film in the second recess and including the first high-k dielectric material in a second concentration that is greater than the first concentration, and the second high-k dielectric material; a first metal-containing film on the first lower high-k dielectric film and including silicon in a third concentration; and a second metal-containing film on the second lower high-k dielectric film and including silicon in a fourth concentration that is smaller than the third concentration.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Yeol Song, Su Young Bae, Dong Soo Lee, Hyung Suk Jung, Sang Jin Hyun
  • Publication number: 20200035842
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Application
    Filed: August 6, 2019
    Publication date: January 30, 2020
    Inventors: Jae-Jung KIM, Dong-Soo LEE, Sang-Yong KIM, Jin-Kyu JANG, Won-Keun CHUNG, Sang-Jin HYUN
  • Patent number: 10529699
    Abstract: Provided are a light source module and a backlight unit (BLU) including the same. The light source module includes a substrate including a base plate extending in a first direction and a pair of dam structures stacked on opposing sides of the base plate along a second direction, orthogonal to the first direction, and extending along the base plate in the first direction, wherein the pair of dam structures are spaced apart from each other along a third direction, orthogonal to the first and second directions. A plurality of light-emitting devices are mounted on the substrate between the pair of dam structures and spaced apart from one another in the first direction. An encapsulation layer covers at least one side surface and a top surface of each of the plurality of light-emitting devices. A height of the pair of dam structures is greater than a height of the encapsulation layer.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-jun Bang, Seog-ho Lim, Chang-ho Shin, Dong-soo Lee, Sun Kim
  • Patent number: 10529817
    Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yeol Song, Wan-don Kim, Su-young Bae, Dong-soo Lee, Jong-han Lee, Hyung-suk Jung, Sang-jin Hyun
  • Patent number: 10509159
    Abstract: A light source module according to some example embodiments includes a first substrate and a plurality of second substrates. The first substrate includes a plurality of connectors configured to at least receive a supply of electrical power and a plurality of first connection pads that are configured to be electrically connected to the plurality of connectors. The second substrates each include a plurality of mounting elements on an upper surface and a plurality of second connection pads on a lower surface of the second substrate and configured to be electrically connected to the plurality of mounting elements. Each mounting element may be connected to a separate light-emitting device. A plurality of connection members may electrically connect the first connection pads of the first substrate to the plurality of second connection pads of the plurality of second substrates.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: December 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-soo Lee, Seog-ho Lim, Chang-ho Shin, Sun Kim, Myoung-sun Ha, Jae-jun Bang
  • Publication number: 20190363084
    Abstract: A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.
    Type: Application
    Filed: December 12, 2018
    Publication date: November 28, 2019
    Inventors: Min-Seok JO, Jae-Hyun LEE, Jong-Han LEE, Hong-Bae PARK, Dong-Soo LEE
  • Publication number: 20190311302
    Abstract: An electronic apparatus is provided. The electronic apparatus includes a first memory configured to store a first artificial intelligence (AI) model including a plurality of first elements and a processor configured to include a second memory. The second memory is configured to store a second AI model including a plurality of second elements. The processor is configured to acquire output data from input data based on the second AI model. The first AI model is trained through an AI algorithm. Each of the plurality of second elements includes at least one higher bit of a plurality of bits included in a respective one of the plurality of first elements.
    Type: Application
    Filed: October 5, 2018
    Publication date: October 10, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-hoon KIM, Young-hwan PARK, Dong-soo LEE, Dae-hyun KIM, Han-su CHO, Hyun-jung KIM
  • Patent number: 10381490
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 13, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Jung Kim, Dong-Soo Lee, Sang-Yong Kim, Jin-Kyu Jang, Won-Keun Chung, Sang-Jin Hyun
  • Publication number: 20190218598
    Abstract: A graphene nanosensor is capable of: simply, quickly and accurately detecting RNA biomarkers that have disease-specific over-expression, as well as an expression level thereof, in living tissues or cells; obtaining a product with high reliability and resolution. The graphene nanosensor enables rapid diagnosis of a disease and being helpful for establishing treatment policy of the disease. The graphene nanosensor may rapidly and simply detect a target RNS with high sensitivity at low costs, thereby expecting superior effects when used in clinical applications and thus replacing the FISH method.
    Type: Application
    Filed: August 10, 2017
    Publication date: July 18, 2019
    Inventors: Do Won HWANG, Dong Soo LEE, Yoo Ri CHOI, Mi Young KIM