Abstract: A semiconductor memory apparatus includes a first comparison block configured to compare a plurality of channel data with one another and generate a first comparison signal, or output one of the plurality of channel data as the first comparison signal, in response to a plurality of channel select signals; a second comparison block configured to compare the plurality of channel data and generate a second comparison signal when the plurality of channel select signals have a predetermined combination and a channel detection signal has a predetermined logic level; a channel selection detection block configured to enable the channel detection signal when only one channel select signal among the plurality of channel select signals is enabled; and a combined output block configured to enable a test result signal when at least one comparison signal of the first and second comparison signals is enabled.

Abstract: A semiconductor memory device may include: a memory cell array; a first address controller configured to receive a first command and a first address and generate a first control signal in response to the first command; and a second address controller configured to receive a second address and a second command inputted at the same time as the first command, and generate a second control signal in response to the second command.

Abstract: A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.

Abstract: A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

Abstract: Methods of manufacturing a resistance change layer and a resistive random access memory device are provided. The method of manufacturing a resistance change layer includes forming a preliminary resistance change layer including an oxide semiconductor material on a substrate and irradiating the preliminary resistance change layer with an electron beam to a predetermined depth. On a path along which the electron beam is irradiated, a composition ratio of the resistance change layer changes in a direction in which a density of oxygen vacancies of the oxide semiconductor material increases. Accordingly, the composition ratio of a resistance change layer is easily controlled using electron beam irradiation. In addition, since interfacial surface roughness and internal defect structures of an oxide semiconductor are controlled by electron beam irradiation, a resistance change ratio is improved and thereby device characteristics can be improved.

Abstract: An output timing control circuit of a semiconductor apparatus may include a strobe signal generation path configured to control a latency and a delay time of an internal signal, and generate a strobe signal. The output timing control circuit may include a first detection block configured to detect a phase difference of the strobe signal and a clock signal, and control the delay time according to the detected phase difference. The output timing control circuit may include a second detection block configured to detect a latency difference of the strobe signal and the internal signal, and control the latency according to the detected latency difference. The internal signal may be generated according to a preset timing of a command received by the strobe signal generation path.

Abstract: A semiconductor integrated circuit includes a test input/output port including test pads; an internal input interface configured to generate an internal clock, an internal address, an internal command, internal data and temporary storage data in response to external signals through the test input/output port; and an error detection block configured to determine whether the internal data and the temporary storage data are the same, and output a result through one test pad of the port. The internal input interface includes a data input/output block which generates the internal data and the data input/output block includes a temporary storage part which stores the internal data as the temporary storage data, a data output part which receives the temporary storage data, and a data input part which receives an output of the data output part and outputs it as the internal data.

Abstract: A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

Abstract: A plurality of memory blocks; and a control block configured to independently operate a part of the plurality of memory banks as a first sub-channel and a remainder of the plurality of memory banks as a second sub-channel according to whether a sub-channel is set.

Abstract: Disclosed is a method and apparatus for manufacturing a melt-blown fabric web, by which a melt-blown fabric web having improved filament cohesion and excellent bulky characteristics and sound-absorbing performance is manufactured. The apparatus includes a heat extruder for heating a thermoplastic resin composition and extruding the melted thermoplastic resin, a melt-blown fiber spinner for spinning the extruded thermoplastic resin as a melt-blown fiber in a filament form, a variable gas injector for injecting gas whose injection speed and injection quantity are continuously changed at random to the melt-blown fiber spun from the melt-blown fiber spinner to cause the injected gas to collide with the spun melt-blown fiber, and a collector for collecting the melt-blown fiber, which is spun from the melt-blown fiber spinner and collides with the gas, to form a melt-blown fabric web.

Abstract: A test circuit includes a through via test unit configured to be set to a first resistance value in response to a first test control signal and to a second resistance value in response to the first test control signal and a second test control signal, and form a current path including a through via that electrically connects a first chip and a second chip; and a test measurement unit configured to supply a test voltage to the through via and measure a current flowing through the through via.

Abstract: A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips may include a plurality of through-vias, each formed at a corresponding location in the plurality of through-vias, and each of the plurality of through-vias is electrically coupled with a through-via in a neighboring stacked chip in a diagonal direction. The semiconductor apparatus includes a plurality of through-via arrays, and performs repair operation with a unit of the through-via array.

Abstract: A test circuit includes a through via test unit configured to be set to a first resistance value in response to a first test control signal and to a second resistance value in response to the first test control signal and a second test control signal, and form a current path including a through via that electrically connects a first chip and a second chip; and a test measurement unit configured to supply a test voltage to the through via and measure a current flowing through the through via.

Abstract: A memory device includes a first memory block suitable for transmitting and receiving signals through a first channel, a second memory block suitable for transmitting and receiving signals through a second channel, and a test control unit suitable for applying a first command signal among a plurality of command signals to the first and second channels at different values, while applying the plurality of command signals from an exterior of the memory device to the first and second channels in a test operation, wherein the first command signal distinguishes write and read operations of the first and second memory blocks, wherein, when the first memory block performs a read operation in the test operation, the second memory block performs a write operation, and data outputted from the first memory block is inputted to the second memory block.

Abstract: The present invention relates to a printed circuit board which includes: a solder pad on which a solder ball is mounted; an insulator formed on the solder pad; and a protrusion formed under the insulator to support the solder ball when mounting the solder ball and can stably mount the solder ball.

Abstract: The present invention relates to a semiconductor memory circuit enabling stable data transmission in a high frequency operation and a data processing system using the same. The data processing system includes a semiconductor memory circuit configured to output data, corresponding to a read command, in response to an external strobe signal, and a controller configured to provide the semiconductor memory circuit with the read command and the strobe signal related to the read command.

Abstract: A dock controller may include a dock period detector suitable for delaying a first dock signal through a plurality of unit delay circuits, and outputting a detection signal by detecting a period of the first dock signal as the number of unit delay circuits used for unit delay of the first clock signal among the unit delay circuits; and a clock generator suitable for generating a delay clock signal delayed by a half period of the first dock signal in response to the detection signal outputted from the clock period detector, and generating a second clock signal having a period corresponding to edges of the first clock signal and the delay clock signal.

Abstract: A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.

Abstract: A semiconductor memory device may include: a memory cell array; a first address controller configured to receive a first command and a first address and generate a first control signal in response to the first command; and a second address controller configured to receive a second address and a second command inputted at the same time as the first command, and generate a second control signal in response to the second command.

Abstract: A plurality of memory blocks; and a control block configured to independently operate a part of the plurality of memory banks as a first sub-channel and a remainder of the plurality of memory banks as a second sub-channel according to whether a sub-channel is set.