Abstract: A memory device includes: a plurality of first lines; a plurality of second lines; a plurality of bank groups each including a predetermined number of banks; and a column signal transmission unit suitable for transmitting one or more column command signals and one or more column address signals to the bank groups through the first lines based on an odd-numbered column command, and transmitting the column command signals and the column address signals to the bank groups through the second lines based on an even-numbered column command.

Abstract: A semiconductor memory apparatus includes a first comparison block configured to compare a plurality of channel data with one another and generate a first comparison signal, or output one of the plurality of channel data as the first comparison signal, in response to a plurality of channel select signals; a second comparison block configured to compare the plurality of channel data and generate a second comparison signal when the plurality of channel select signals have a predetermined combination and a channel detection signal has a predetermined logic level; a channel selection detection block configured to enable the channel detection signal when only one channel select signal among the plurality of channel select signals is enabled; and a combined output block configured to enable a test result signal when at least one comparison signal of the first and second comparison signals is enabled.

Abstract: A memory device includes: a plurality of first lines; a plurality of second lines; a plurality of bank groups each including a predetermined number of banks; and a column signal transmission unit suitable for transmitting one or more column command signals and one or more column address signals to the bank groups through the first lines based on an odd-numbered column command, and transmitting the column command signals and the column address signals to the bank groups through the second lines based on an even-numbered column command.

Abstract: A memory chip may include a plurality of channels including a plurality of memory banks and having a separate input/output interface, and each of the plurality of channels may be configured to simultaneously latch compression data groups obtained by compressing respective unit data groups outputted from the plurality of memory banks, sequentially output latched data as test read data according to a read start signal or a read end signal, and generate the read end signal which defines that final data output has ended.

Abstract: An apparatus for blending a polyethylene terephthalate (PET) and a kapok fiber using static electricity is provided, along with a method for blending the PET fiber and the kapok fiber using the apparatus. The fiber blending apparatus includes a fiber blending chamber having an inlet in which the PET fiber and the kapok fiber are introduced and an outlet from which a nonwoven fabric is discharged. A discharge plate is positioned at an upper side and a lower side based on a center line passing through the center of a cross section of the fiber blending chamber to accumulate the static electricity. The PET fiber and the kapok fiber contacting the discharge plate are electrically charged and are thus uniformly distributed and blended around the center line and stacked around an outlet.

Abstract: Package substrate and a method of manufacturing the same is disclosed. The package substrate includes an insulating layer having first circuit patterns embedded in a first surface of the insulating layer, and a protruded circuit pattern formed above at least one of the embedded first circuit patterns, wherein a width of the protruded circuit pattern is greater than a width of each of the embedded first circuit patterns. Accordingly, a flip chip and a wire bonding chip may be installed at the same time owing to an embedded structure of circuit pattern and a protruded structure of circuit pattern realized together on a surface where an electronic component is to be installed. Moreover, a fine circuit pattern may be formed, and a surface treatment layer may be selectively formed at desired portions without forming an additional seed layer for electroplating, thereby possibly simplifying manufacturing processes and saving manufacturing costs.

Abstract: A fibrous component for a vehicle exterior includes a skin layer having a multilayer structure comprising a laminated web including a reinforcing fiber and a binder fiber, the skin layer including pores that absorb sound; a sound absorbing pad layer disposed on an inner side of the skin layer and absorbing sound; and an adhesive layer disposed between the skin layer and the sound absorbing pad layer. The adhesive layer adheres the skin layer and the sound absorbing layer to each other.

Abstract: A stack memory device may include a core chip and a base chip. The core chip may include a data receiver, a strobe signal generation unit, and a test register. The data receiver may be configured for receiving data outputted from the core chip through a first normal port. The strobe signal generation unit may be configured to generate a data strobe signal based on one of a normal strobe signal and a test strobe signal depending on an operation mode. The test register may store data outputted from the data receiver in response to the data strobe signal.

Abstract: A test circuit includes a through via test unit configured to be set to a first resistance value in response to a first test control signal and to a second resistance value in response to the first test control signal and a second test control signal, and form a current path including a through via that electrically connects a first chip and a second chip; and a test measurement unit configured to supply a test voltage to the through via and measure a current flowing through the through via.

Abstract: A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.

Abstract: An electronic component embedded printed circuit board and method thereof a first insulation layer, an electronic component, a second insulation layer, and a circuit layer. The first insulation layer includes a trench formed therein. The electronic component is installed in the trench. The second insulation layer is formed above the first insulation layer and the electronic component. The circuit layer is formed on the first insulation layer and on the second insulation layer.

Abstract: A stack memory device may include a core chip and a base chip. The core chip may include a data receiver, a strobe signal generation unit, and a test register. The data receiver may be configured for receiving data outputted from the core chip through a first normal port. The strobe signal generation unit may be configured to generate a data strobe signal based on one of a normal strobe signal and a test strobe signal depending on an operation mode. The test register may store data outputted from the data receiver in response to the data strobe signal.

Abstract: Disclosed herein are a printed circuit board (PCB) and a method of manufacturing the same. The PCB includes a core layer, metal bumps embedded in the core layer, one surface of the metal bumps being opened to the outside, and a solder resist layer including an opening is manufactured by a separating substrate manufacture method. In the PCB, empty space between the bumps is filled with an insulating material instead of solder resist, and thus, a problem in terms of an empty space between bumps is addressed without requiring a new solder resist process.

Abstract: A stack memory device may include a core chip and a base chip. The core chip may include a data receiver, a strobe signal generation unit, and a test register. The data receiver may be configured for receiving data outputted from the core chip through a first normal port. The strobe signal generation unit may be configured to generate a data strobe signal based on one of a normal strobe signal and a test strobe signal depending on an operation mode. The test register may store data outputted from the data receiver in response to the data strobe signal.

Abstract: An address input circuit of a semiconductor device includes: an address latch unit configured to generate latch addresses, by latching addresses sequentially provided by an external, according to a command decoding signal, wherein latch timings of each of the addresses are adjusted differently from one another; and a command decoder configured to decode a command provided from the external and generate the command decoding signal.

Abstract: A semiconductor memory apparatus includes a first comparison block configured to compare a plurality of channel data with one another and generate a first comparison signal, or output one of the plurality of channel data as the first comparison signal, in response to a plurality of channel select signals; a second comparison block configured to compare the plurality of channel data and generate a second comparison signal when the plurality of channel select signals have a predetermined combination and a channel detection signal has a predetermined logic level; a channel selection detection block configured to enable the channel detection signal when only one channel select signal among the plurality of channel select signals is enabled; and a combined output block configured to enable a test result signal when at least one comparison signal of the first and second comparison signals is enabled.

Abstract: A semiconductor memory device may include: a memory cell array; a first address controller configured to receive a first command and a first address and generate a first control signal in response to the first command; and a second address controller configured to receive a second address and a second command inputted at the same time as the first command, and generate a second control signal in response to the second command.

Abstract: A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.

Abstract: A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

Abstract: Methods of manufacturing a resistance change layer and a resistive random access memory device are provided. The method of manufacturing a resistance change layer includes forming a preliminary resistance change layer including an oxide semiconductor material on a substrate and irradiating the preliminary resistance change layer with an electron beam to a predetermined depth. On a path along which the electron beam is irradiated, a composition ratio of the resistance change layer changes in a direction in which a density of oxygen vacancies of the oxide semiconductor material increases. Accordingly, the composition ratio of a resistance change layer is easily controlled using electron beam irradiation. In addition, since interfacial surface roughness and internal defect structures of an oxide semiconductor are controlled by electron beam irradiation, a resistance change ratio is improved and thereby device characteristics can be improved.