Patents by Inventor Dong-Uk Lee

Dong-Uk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • VENTILATION APPARATUS CAPABLE OF RECOVERING THERMAL ENERGY
    Publication number: 20130319632
    Abstract: Provided is a ventilation apparatus for a building to recover thermal energy. The ventilation apparatus includes a main body, an absorption filter, a heat exchanger, first and second blowing fans, and a water supply pipe. The main body has air exhaust ports for discharging indoor air out of the building and air supply ports for supplying outdoor air into the building. The absorption filter is disposed in the main body to cool exhaust air. The heat exchanger is disposed in the main body to exchange heat between supply air and exhaust air. The first and second blowing fans are disposed in the main body. The first blowing fan discharges indoor air and the second blowing fan supplies outdoor air. The water supply pipe supplies water to the absorption filter.
    Type: Application
    Filed: February 23, 2012
    Publication date: December 5, 2013
    Inventor: Dong Uk Lee
  • Semiconductor device and system
    Patent number: 8593892
    Abstract: A system includes a data transmitting device and a data receiving device. The data transmitting device includes a data strobe signal generation unit configured to generate first and second data strobe signals in response to an output enable signal, and a data output unit configured to transmit data in synchronization with the first data strobe signal. The data receiving device is configured to receive the data in synchronization with the second data strobe signal.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 26, 2013
    Assignee: SK hynix Inc.
    Inventor: Dong Uk Lee
  • METHOD AND APPARATUS FOR MANUFACTURING MELT-BLOWN FABRIC WEB HAVING RANDOM AND BULKY CHARACTERISTICS
    Publication number: 20130285275
    Abstract: Disclosed is a method and apparatus for manufacturing a melt-blown fabric web, by which a melt-blown fabric web having improved filament cohesion and excellent bulky characteristics and sound-absorbing performance is manufactured. The apparatus includes a heat extruder for heating a thermoplastic resin composition and extruding the melted thermoplastic resin, a melt-blown fiber spinner for spinning the extruded thermoplastic resin as a melt-blown fiber in a filament form, a variable gas injector for injecting gas whose injection speed and injection quantity are continuously changed at random to the melt-blown fiber spun from the melt-blown fiber spinner to cause the injected gas to collide with the spun melt-blown fiber, and a collector for collecting the melt-blown fiber, which is spun from the melt-blown fiber spinner and collides with the gas, to form a melt-blown fabric web.
    Type: Application
    Filed: August 27, 2012
    Publication date: October 31, 2013
    Applicants: HYUNDAI MOTOR COMPANY, SUN JIN INDUSTRY CO., LTD., IKSUNG CO., LTD., KIA MOTORS CORPORATION
    Inventors: Jung Wook Lee, Gi Won Kim, Hyeon Ho Kim, Won Jin Seo, Dong Uk Lee, Moon Soo Lim, Min Su Kim, Jin Ho Hwang, Ki Wook Yang, In Hee Song
  • CONVERGENCE SOUND-ABSORBING MATERIAL AND METHOD OF FABRICATING THE SAME
    Publication number: 20130277146
    Abstract: Disclosed is a convergence sound-absorbing material and a method of fabricating the same, and more particularly, a convergence sound-absorbing material and a method of fabricating the same in which an inexpensive eco-friendly recycled filler composed of polyurethane foam and a recycled thread or waste felt is used as a filler in an intermediate layer of the PET sound-absorbing material to provide remarkably reduced fabrication costs and excellent sound-absorbing performance. In addition the waste felt, which is typically discarded during a process of cutting the sound-absorbing material, is recycled for use in the filler.
    Type: Application
    Filed: September 27, 2012
    Publication date: October 24, 2013
    Applicants: HYUNDAI MOTOR COMPANY, YOUNGSEUNG CO., LTD., DAEHAN SOLUTION CO., LTD., KIA MOTORS CORPORATION
    Inventors: Jung Wook Lee, Dong Uk Lee, Jin Ho Hwang, Hoe Hyun Kwon, Jung Hoi Choi
  • Laser scanning display and beam alignment method thereof
    Patent number: 8562153
    Abstract: A laser scanning display including a micro scanning mirror, and a beam alignment method thereof are disclosed. A scanning display includes a frame, at least one light source fixedly secured to the frame, a lens positioned in front of a light emission surface of the light source, the lens having a holder detachably mounted to an external adjusting device which is to make fine adjustment to finish beam alignment, and a fastening portion for fastening the lens having beam alignment finished thus to the frame.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: October 22, 2013
    Assignee: LG Electronics Inc.
    Inventors: Sang Keun Lee, Dong Uk Lee, Jae Wook Kwon
  • SEMICONDUCTOR MEMORY CIRCUIT AND DATA PROCESSING SYSTEM USING THE SAME
    Publication number: 20130265835
    Abstract: The present invention relates to a semiconductor memory circuit enabling stable data transmission in a high frequency operation and a data processing system using the same. The data processing system includes a semiconductor memory circuit configured to output data, corresponding to a read command, in response to an external strobe signal, and a controller configured to provide the semiconductor memory circuit with the read command and the strobe signal related to the read command.
    Type: Application
    Filed: September 1, 2012
    Publication date: October 10, 2013
    Applicant: SK HYNIX INC.
    Inventor: Dong Uk LEE
  • TEST CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    Publication number: 20130265033
    Abstract: A test circuit includes a through via test unit configured to be set to a first resistance value in response to a first test control signal and to a second resistance value in response to the first test control signal and a second test control signal, and form a current path including a through via that electrically connects a first chip and a second chip; and a test measurement unit configured to supply a test voltage to the through via and measure a current flowing through the through via.
    Type: Application
    Filed: September 5, 2012
    Publication date: October 10, 2013
    Applicant: SK HYNIX INC.
    Inventors: Dong Uk LEE, Young Ju KIM
  • Apparatus and method for outputting data of semiconductor memory apparatus
    Patent number: 8508273
    Abstract: An apparatus for outputting data of a semiconductor memory apparatus, which is capable of varying the slew rate and the data output timing, includes a bias generator that generates a bias having a level corresponding to a set value, a slew rate controller that controls a pull-up slew rate or a pull-down slew rate of input data on the basis of the bias generated by the bias generator, and a data outputting unit that outputs data on the basis of the slew rate controlled by the slew rate controller. Therefore, it is possible to satisfy various operational conditions without changing the structure of the circuit and to correspond rapidly and appropriately whit a change in the system, which enables the applied range of the products to be extended.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong-Uk Lee
  • Burst order control circuit
    Patent number: 8498175
    Abstract: A burst order control circuit includes a signal transmitting unit transmitting a second address as first and second signals in response to a mode signal and a first address, a signal delay unit delaying a read command, the first signal, and the second signal to generate a delayed read command, a first delayed signal, and a second delayed signal, a signal generating unit configured to generate a burst signal in response to the first address and generate first and second transmission signals in response to the delayed read command and the first and second delayed signals, and an output unit sorting and outputting a plurality of data in response to the burst signal, the first transmission signal, and the second transmission signal.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: July 30, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong-Uk Lee
  • Output driver
    Patent number: 8493100
    Abstract: An output driver includes a control signal generation unit configured to generate a control signal in response to a driving strength signal and a power supply voltage level, and a driving signal generation unit configured to buffer a pre-driving signal and generate a driving signal for driving an output data, wherein a driving strength of the driving signal is adjusted in response to the control signal.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: July 23, 2013
    Assignee: SK Hynix Inc.
    Inventors: Ji Yeon Yang, Dong Uk Lee
  • Data output circuit of semiconductor apparatus
    Patent number: 8446174
    Abstract: A data output circuit of a semiconductor apparatus includes a clock skew compensation repeater configured to control a delay amount of a clock in response to skew compensation codes and output a data synchronization clock; a mismatch compensation driver configured to synchronize internal data with the data synchronization clock and output the internal data synchronized with the data synchronization clock by controlling a transition timing of the internal data according to mismatch compensation codes; and a data output driver configured to generate output data in response to an output of the mismatch compensation driver.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: May 21, 2013
    Assignee: SK Hynix Inc.
    Inventor: Dong Uk Lee
  • Input buffer capable of expanding an input level range
    Patent number: 8436661
    Abstract: An input buffer includes a first amplification block, a second amplification block, and a buffer block. The first amplification block is configured to be driven by an external voltage, to differentially amplify an input signal and a reference voltage in response to a bias voltage, and to subsequently generate first and second differential signals. The second amplification block is configured to be driven by an internal voltage, to differentially amplify the first and second differential signals, and to generate an output signal. The buffer block is configured to be driven by the internal voltage, to buffer the output signal, and to output an inverted output signal.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: May 7, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong Uk Lee
  • SEMICONDUCTOR APPARATUS
    Publication number: 20130093099
    Abstract: A semiconductor apparatus having first and second chips stacked upon each other includes first, second and third through vias positioned on a same vertical lines in the first and second chips and formed through the first and second chips. A first input/output circuit connected with the second through via of the first chip. A second input/output circuit connected with the second through via of the second chip. The second through via of the second chip is connected with the first through via of the first chip.
    Type: Application
    Filed: April 12, 2012
    Publication date: April 18, 2013
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sang Hoon SHIN, Dong Uk LEE
  • Delay locked loop semiconductor apparatus that models a delay of an internal clock path
    Patent number: 8373480
    Abstract: A delay locked loop semiconductor apparatus that models a delay of an internal clock path is presented. The semiconductor apparatus includes: a DLL and a detection code output block. The DLL includes a delay model unit in which a delay value of an internal clock path is modeled and is configured to output a DLL clock signal of which the phase is controlled by reflecting the delay value of the internal clock path into an applied input clock signal. The detection code output block is configured to output a phase difference detection code having a code value corresponding to a phase difference between a first phase correction clock signal generated by reflecting a model delay value of the delay model unit into the DLL clock signal and a second phase correction clock signal generated by reflecting an actual delay value of the internal clock path into the DLL clock signal.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 12, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong Uk Lee
  • Decay heat removal system comprising heat pipe heat exchanger
    Patent number: 8300759
    Abstract: Disclosed herein is a decay heat removal system, including: a decay heat exchanger that absorbs decay heat generated by a nuclear reactor; a heat pipe heat exchanger that receives the decay heat from the decay heat exchanger through a sodium loop for heat removal and then discharges the decay heat to the outside; and a sodium-air heat exchanger that is connected to the heat pipe heat exchanger through the sodium loop and discharges the decay heat transferred thereto through the sodium loop to the outside. According to the decay heat removal system, a heat removal capability can be realized by the heat pipe heat exchanger at such a high temperature at which the safety of a nuclear reactor is under threat, and a cooling effect can be obtained through the sodium-air heat exchanger at a temperature lower than that temperature.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: October 30, 2012
    Assignees: Korea Atomic Energy Research Institute, Korea Hydro and Nuclear Power Co., Ltd
    Inventors: Hae Yong Jeong, Chungho Cho, Yong Bum Lee, Dong Uk Lee, Jae Hyuk Eoh, Kwi Seok Ha
  • DELAY LOCKED LOOP SEMICONDUCTOR APPARATUS THAT MODELS A DELAY OF AN INTERNAL CLOCK PATH
    Publication number: 20120256667
    Abstract: A delay locked loop semiconductor apparatus that models a delay of an internal clock path is presented. The semiconductor apparatus includes: a DLL and a detection code output block. The DLL includes a delay model unit in which a delay value of an internal clock path is modeled and is configured to output a DLL clock signal of which the phase is controlled by reflecting the delay value of the internal clock path into an applied input clock signal. The detection code output block is configured to output a phase difference detection code having a code value corresponding to a phase difference between a first phase correction clock signal generated by reflecting a model delay value of the delay model unit into the DLL clock signal and a second phase correction clock signal generated by reflecting an actual delay value of the internal clock path into the DLL clock signal.
    Type: Application
    Filed: June 19, 2012
    Publication date: October 11, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Dong Uk LEE
  • DATA OUTPUT CIRCUIT OF SEMICONDUCTOR APPARATUS
    Publication number: 20120250734
    Abstract: A data output circuit of a semiconductor apparatus includes a clock skew compensation repeater configured to control a delay amount of a clock in response to skew compensation codes and output a data synchronization clock; a mismatch compensation driver configured to synchronize internal data with the data synchronization clock and output the internal data synchronized with the data synchronization clock by controlling a transition timing of the internal data according to mismatch compensation codes; and a data output driver configured to generate output data in response to an output of the mismatch compensation driver.
    Type: Application
    Filed: October 28, 2011
    Publication date: October 4, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Dong Uk LEE
  • Fuel reforming apparatus and manufacturing method thereof
    Patent number: 8273141
    Abstract: A fuel reforming apparatus including reaction substrates is provided. The reaction substrates of the present invention is made of stainless steel, nickel steel, or chromium steel. Each of the reaction substrates has a channel formed on the surface of the reaction substrate. Reactant for oxidation reaction or for fuel reforming reaction flow through the channel. A catalyst containing layer is formed on the surface of the channel by directly oxidizing the surface of the channel. Therefore, the catalyst containing layer is formed with oxidized steel. A catalyst layer is formed on the catalyst containing layer. A pair of substrates can be laminated to make one substrate a thermal source unit and another a reforming reaction unit.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: September 25, 2012
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Sung-Chul Lee, Ju-Yong Kim, Chan-Ho Lee, Man-Seok Han, Yong-Kul Lee, Dong-Myung Suh, Dong-Uk Lee, Jin-Kwang Kim, Jin-Goo Ahn, Leonid Gorobinskiy
  • BURST ORDER CONTROL CIRCUIT
    Publication number: 20120188827
    Abstract: A burst order control circuit includes a signal transmitting unit transmitting a second address as first and second signals in response to a mode signal and a first address, a signal delay unit delaying a read command, the first signal, and the second signal to generate a delayed read command, a first delayed signal, and a second delayed signal, a signal generating unit configured to generate a burst signal in response to the first address and generate first and second transmission signals in response to the delayed read command and the first and second delayed signals, and an output unit sorting and outputting a plurality of data in response to the burst signal, the first transmission signal, and the second transmission signal.
    Type: Application
    Filed: May 26, 2011
    Publication date: July 26, 2012
    Inventor: Dong-Uk LEE
  • Delay locked loop semiconductor apparatus that models a delay of an internal clock path
    Patent number: 8222938
    Abstract: A delay locked loop semiconductor apparatus that models a delay of an internal clock path is presented. The semiconductor apparatus includes: a DLL and a detection code output block. The DLL includes a delay model unit in which a delay value of an internal clock path is modeled and is configured to output a DLL clock signal of which the phase is controlled by reflecting the delay value of the internal clock path into an applied input clock signal. The detection code output block is configured to output a phase difference detection code having a code value corresponding to a phase difference between a first phase correction clock signal generated by reflecting a model delay value of the delay model unit into the DLL clock signal and a second phase correction clock signal generated by reflecting an actual delay value of the internal clock path into the DLL clock signal.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: July 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong Uk Lee