Patents by Inventor Dongfang Wang
Dongfang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240363641Abstract: A display substrate, a manufacturing method therefor, and a display device are provided.Type: ApplicationFiled: June 30, 2022Publication date: October 31, 2024Inventors: Dongfang WANG, Wei LIU, Hehe HU, Lizhong WANG, Ce NING
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Patent number: 12130498Abstract: The present disclosure discloses an optical lens assembly including a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens and a seventh lens, which are arranged sequentially from an object side to an image side along an optical axis. The first lens has negative refractive power, an object-side surface thereof is convex, and an image-side surface thereof is concave. The second lens has negative refractive power, an object-side surface thereof is convex, and an image-side surface thereof is concave. The third lens has positive refractive power, and both of an object-side surface and an image-side surface thereof are convex. The fourth lens has refractive power. The fifth lens and the sixth lens are cemented to form a cemented lens. The seventh lens has positive refractive power, and both of an object-side surface and an image-side surface thereof are convex.Type: GrantFiled: November 27, 2020Date of Patent: October 29, 2024Assignee: NINGBO SUNNY AUTOMOTIVE OPTECH CO., LTDInventors: Bo Yao, Dongfang Wang
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Publication number: 20240329478Abstract: An array substrate and a manufacturing method therefor, and a display apparatus are provided. The array substrate includes an underlay substrate, and at least one first transistor, at least one data line and at least one pixel electrode disposed on the underlay substrate. The at least one first transistor includes a first active layer and a first gate; the first gate is located on a side of the first active layer away from the underlay substrate, and orthographic projections of the first gate and the first active layer on the underlay substrate are at least partially overlapped. The first active layer is electrically connected to the data line and the pixel electrode, respectively. The data line is located on a side of the first active layer close to the underlay substrate, and the pixel electrode is located on a side of the first gate away from the underlay substrate.Type: ApplicationFiled: April 18, 2024Publication date: October 3, 2024Inventors: Guangcai YUAN, Hehe HU, Ce NING, Hui GUO, Fengjuan LIU, Dongfang WANG, Zhengliang LI, Jiayu HE
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Patent number: 12105262Abstract: The present disclosure discloses an optical lens assembly and an electronic device including the optical lens assembly. The optical lens assembly includes, sequentially from an object side to an image side along an optical axis, a first lens, a second lens, a third lens, a fourth lens and a fifth lens. The first lens has negative refractive power; the second lens has positive refractive power; the third lens has positive refractive power, and both of an object-side surface and an image-side surface of the third lens are convex; the fourth lens has negative refractive power, and both of an object-side surface and an image-side surface of the fourth lens are concave; and the fifth lens has refractive power. The optical lens assembly may achieve at least one of the beneficial effects of high resolution, miniaturization, small aperture, small CRA, and good temperature performance and the like.Type: GrantFiled: May 18, 2021Date of Patent: October 1, 2024Assignee: NINGBO SUNNY AUTOMOTIVE OPTECH CO., LTDInventors: Ludong Zhang, Dongfang Wang, Bo Yao
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Publication number: 20240324336Abstract: A display panel includes a substrate, an insulating layer, a metal layer, a first transparent conductive layer and a second transparent conductive layer. The insulating layer has at least one via hole in each of a second sub-pixel region and a fourth sub-pixel region. The first transparent conductive layer includes a plurality of first transparent conductive lines. The second transparent conductive layer includes a Plurality of second transparent conductive lines. A total overlapping area between an orthographic projection of a first transparent conductive line on the substrate and orthogonal projections, on the substrate, of all via holes, in the second sub-pixel region, of the insulating layer is less than a total overlapping area between an orthographic projection of a second transparent conductive line on the substrate and orthogonal projections, on the substrate, of all via holes, in the fourth sub-pixel region, of the insulating layer.Type: ApplicationFiled: March 1, 2022Publication date: September 26, 2024Inventors: Dongfang YANG, Yao HUANG, Yue LONG, Zhuoran YAN, Benlian WANG, Yuanjie XU, Binyan WANG
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Publication number: 20240306438Abstract: Provided are an array substrate and a method for manufacturing the array substrate, a display panel and a display device, belonging to the field of display technologies. The array substrate includes a base substrate and a driving thin-film transistor disposed on the base substrate. The driving thin-film transistor includes a first gate, a first insulating layer, a first active layer, a second insulating layer, and a first source/drain electrode which are sequentially laminated on the base substrate. The thickness of the first insulating layer is greater than the thickness of the second insulating layer. Therefore, the regulating ability of the first gate of the driving thin-film transistor over the first active layer is reduced, and the subthreshold swing of the driving thin-film transistor is increased, thereby improving the adjusting ability of the driving thin-film transistor over the grayscale of the light-emitting device on the display panel.Type: ApplicationFiled: December 29, 2021Publication date: September 12, 2024Inventors: Dongfang WANG, Wei LIU, Jie HUANG
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Publication number: 20240297256Abstract: An array base plate includes a substrate; and a driving transistor and a switching transistor that are located on the substrate; the driving transistor includes a semiconductor layer; the switching transistor includes an active layer and a protecting layer, and the active layer includes two opposite main surfaces and a side surface that is located between outer contours of the two main surfaces; the protecting layer is located on a main surface of the active layer that is away from the substrate and covers the main surface and the side surface; the protecting layer and the semiconductor layer are arranged in a same layer, and a material of the protecting layer and a material of the semiconductor layer are a same metal-oxide-semiconductor material; and a carrier mobility of the protecting layer is less than a carrier mobility of the active layer.Type: ApplicationFiled: November 29, 2021Publication date: September 5, 2024Inventors: Dongfang WANG, Lizhong WANG, Ce NING
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Publication number: 20240295784Abstract: A display substrate, a display panel and a display apparatus. The display substrate includes a first base substrate; a plurality of gate lines and a plurality of data lines which are arranged on a side of the first base substrate; the plurality of gate lines and the plurality of data lines are arranged to be intersected with each other and insulated from each other; a planarization layer, arranged on a side of the gate lines and the data lines away from the first base substrate, and including a first via hole; and a supporting structure, arranged on a side of the planarization layer away from the first base substrate and filled into the first via hole; and in a direction perpendicular to the first base substrate, a height of the supporting structure is greater than a depth of the first via hole.Type: ApplicationFiled: June 22, 2022Publication date: September 5, 2024Inventors: Lizhong WANG, Ce NING, Dongfang WANG, Hui GUO
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Publication number: 20240290890Abstract: A thin film transistor including a base substrate, and a drain, a source and an active layer on the base substrate, where the drain and the source are in different layers, respectively, and any two of an orthographic projection of the drain on the base substrate, an orthographic projection of the source on the base substrate and an orthographic projection of the active layer on the base substrate at least partially overlap each other.Type: ApplicationFiled: March 31, 2022Publication date: August 29, 2024Inventors: Dongfang WANG, Lizhong WANG, Ce NING
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Patent number: 12061317Abstract: The present disclosure discloses an optical lens assembly which includes, sequentially from an object side to an image side along an optical axis, a first lens, a second lens, a third lens, a fourth lens, a fifth lens and a sixth lens. The first lens may have negative refractive power, a convex object-side surface, and a concave image-side surface. The second lens may have negative refractive power, a convex object-side surface, and a concave image-side surface. The third lens may have positive refractive power, and both object-side and image-side surfaces thereof are convex. The fourth lens may have positive refractive power, and both object-side and image-side surfaces thereof are convex. The fifth lens may have negative refractive power, and both object-side and image-side surfaces thereof are concave. The sixth lens may have positive refractive power, and both object-side and image-side surfaces thereof are convex.Type: GrantFiled: October 27, 2020Date of Patent: August 13, 2024Assignee: NINGBO SUNNY AUTOMOTIVE OPTECH CO., LTDInventors: Dongfang Wang, Bo Yao, Ludong Zhang
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Patent number: 12062305Abstract: A test circuit includes a plurality of first switch units and a plurality of second switch units. The first switch units are provided in one-to-one correspondence with a plurality of signal lines. First terminals of the first switch units are connected to first ends of the plurality of signal lines, second terminals of the first switch units are short-circuited to one another, and control terminals of the first switch units are connected to a first control signal terminal. The plurality of second switch units are provided in one-to-one correspondence with the plurality of signal lines. First terminals of the plurality of second switch units are connected to second ends of the plurality of signal lines, second terminals of the plurality of second switch units are short-circuited to one another, and control terminals of the plurality of second switch units are connected to a second control signal terminal.Type: GrantFiled: January 5, 2021Date of Patent: August 13, 2024Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Guangyao Li, Dongfang Wang
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Publication number: 20240250177Abstract: A metal oxide thin film transistor is provided, which includes a metal oxide semiconductor layer, including a first semiconductor layer and a second semiconductor layer, the carrier mobility of the first semiconductor layer is higher than that of the second semiconductor layer; the metal oxide semiconductor layer includes a lower surface, an upper surface and a lateral surface, the source electrode is in contact with the lateral surface and the upper surface; the region where the lateral surface contacts the source electrode or the drain electrode includes a first contact region and a second contact region; which have the shape: a first angle between the lower surface of the metal oxide semiconductor layer and the lateral surface of the first contact region is larger than a second angle between the lower surface of the metal oxide semiconductor layer and the lateral surface of the second contact region.Type: ApplicationFiled: March 31, 2022Publication date: July 25, 2024Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Dapeng XUE, Lizhong WANG, Shuilang DONG, Hehe HU, Nianqi YAO, Guangcai YUAN, Ce NING, Zhengliang LI, Dongfang WANG, Liping LEI, Chen XU, Jie HUANG
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Patent number: 12046723Abstract: A battery, including an electrode assembly including a central hole, at least one positive electrode, at least one negative electrode, and at least one diaphragm separating the at least one positive electrode from the at least one negative electrode. The at least one positive electrode, the at least one negative electrode and the at least one diaphragm are disposed around the central hole in a spiral winding manner. The central hole has a diameter of greater than 0 and smaller than that of the battery. A pin assembly is disposed in the central hole. The pin assembly includes a housing including an axial through hole. The housing is partially or fully disposed in the central hole. At least one integrated circuit device is disposed in the axial through hole. The at least one integrated circuit device includes at least one access terminal and one output terminal.Type: GrantFiled: August 12, 2021Date of Patent: July 23, 2024Assignees: TIANJIN LISHEN BATTERY JOINT-STOCK CO., LTD., TIANJIN JUYUAN NEW ENERGY TECHNOLOGY CO., LTD.Inventors: Nianju Wang, Yuanyuan Ya, Xueheng Jia, Minghui Xu, Dongfang Miao
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Patent number: 12041822Abstract: A display panel having a pixel region includes a base substrate, a plurality of pixel circuits located in the pixel region, and a plurality of light-emitting structures located in the pixel region. Each pixel circuit includes a storage capacitor and a plurality of transistors. The light-emitting structures are configured to emit light of at least three primary colors. Each light-emitting structure includes a light-emitting device. Each pixel circuit is coupled to the light-emitting device in a corresponding light-emitting structure, and a surface of the light-emitting device proximate to the base substrate is a light exit surface. Among the light-emitting structures, an orthogonal projection of an effective light-emitting region, on the base substrate, of the light-emitting device in a first light-emitting structure with a shortest light-emitting wavelength, is spaced apart from orthogonal projections of all storage capacitors of the plurality of pixel circuits on the base substrate.Type: GrantFiled: November 20, 2020Date of Patent: July 16, 2024Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Dongfang Wang, Qinghe Wang
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Time-interleaved successive approximation analog to digital converter and calibration method thereof
Patent number: 12040810Abstract: Provided are a Time-Interleaved Successive Approximation Register Analog-to-Digital Converter, TISAR ADC, and a calibration method thereof. The calibration method for the TISAR ADC may include: sampling an analog signal input into the TISAR ADC to generate a reference digital signal (S130); according to the reference digital signal and output digital signals generated by analog-to-digital conversion sub-modules of the TISAR ADC, obtaining capacitor array calibration parameters and time delay calibration parameters of the analog-to-digital conversion sub-modules; adjusting capacitor arrays of the corresponding analog-to-digital conversion sub-modules according to the capacitor array calibration parameters, respectively; and adjusting time delays of the corresponding analog-to-digital conversion sub-modules according to the time delay calibration parameters, respectively.Type: GrantFiled: October 29, 2020Date of Patent: July 16, 2024Assignee: ZTE CORPORATIONInventors: Yi Wang, Hongxing Zhou, Zhe Zhang, Zuofeng Zhang, Dongfang Ning -
Publication number: 20240234532Abstract: The present disclosure provides a TFT, a manufacturing method and a display substrate, and it relates to the field of TFT technology. The TFT includes: a base substrate; a gate electrode arranged on the base substrate; an active layer arranged at a side of the gate electrode away from the base substrate, an orthogonal projection of the active layer onto the base substrate overlapping with an orthogonal projection of the gate electrode onto the base substrate; and a source electrode and a drain electrode arranged at a side of the active layer away from the base substrate and coupled to the active layer. A resistance between the gate electrode and the drain electrode is greater than a resistance between the gate electrode and the source electrode. According to the present disclosure, it is able to increase a withstand voltage range of the TFT.Type: ApplicationFiled: December 27, 2021Publication date: July 11, 2024Inventors: Hehe HU, Dongfang WANG, Fengjuan LIU, Ce NING, Zhengliang LI, Jiayu HE, Yan QU, Kun ZHAO, Jie HUANG, Liping LEI, Yunsik IM, Shunhang ZHANG, Nianqi YAO, Feifei LI
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Patent number: 12027536Abstract: Provided is a display substrate. The display includes a base substrate, and a pixel unit disposed on the base substrate, wherein the pixel unit includes a storage capacitor, a plate of the storage capacitor being a transparent plate. The pixel unit further comprises an active layer and a source/drain pattern, which are disposed in two different layers.Type: GrantFiled: August 17, 2020Date of Patent: July 2, 2024Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Dongfang Wang, Tongshang Su
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Publication number: 20240212639Abstract: Voltage providing unit, voltage providing method, display driving module and display device are provided. The voltage providing unit, applied to a display panel, is configured to provide a control voltage signal for a driving circuit, and the voltage providing unit includes a buck circuit and a first electrical level converting circuit. The buck circuit is configured to receive a first voltage signal and perform a buck operation on the first voltage signal to obtain a second voltage signal; and the first electrical level converting circuit is connected to the buck circuit, and is configured to receive an input control voltage, a third voltage signal and the second voltage signal, and to generate the control voltage signal in accordance with the input control voltage, the third voltage signal and the second voltage signal, a voltage value of the control voltage signal is less than a predetermined voltage value.Type: ApplicationFiled: September 24, 2021Publication date: June 27, 2024Inventors: Shuilang DONG, Ce NING, Guangcai YUAN, Hehe HU, Lizhong WANG, Nianqi YAO, Dapeng XUE, Liping LEI, Chen XU, Dongfang WANG, Zhengliang LI
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Publication number: 20240213373Abstract: The present disclosure provides a field effect transistor and a method for manufacturing the same, and a display panel, relating to the field of display technologies. The field effect transistor includes a substrate, an active layer, a source, a drain, a first insulating layer and an oxygenating layer. An orthographic projection of the oxygenating layer on the substrate is overlapped with an orthographic projection of a target region of the active layer on the substrate. Therefore, when the oxygenating layer is prepared, oxygen elements in the process environment can diffuse to the target region of the active layer, to oxygenate the active layer. In this way, oxygen vacancies in the active layer can be reduced, and the uniformity and stability of the active layer is improved, thereby further improving the performance of the field effect transistor.Type: ApplicationFiled: November 26, 2021Publication date: June 27, 2024Inventors: Dongfang WANG, Jie HUANG
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Publication number: 20240206308Abstract: The disclosure provides a display panel and a display device. The display panel includes a first substrate and a second substrate, the second substrate has an organic electroluminescent device, an anode layer of the organic electroluminescent device is away from the first substrate and a cathode layer thereof is closer to the first substrate than the anode layer; the cathode layer is electrically connected to an auxiliary electrode on a light entering surface of the first substrate through multiple conductive spacers, the cathode layer is a transparent electrode layer; the auxiliary electrode has a resistance smaller than that of the cathode layer of the organic electroluminescent device; the auxiliary electrode is a grid-shaped auxiliary electrode and in a non-display region, the auxiliary electrode is opaque; the multiple conductive spacers includes first conductive spacers on the auxiliary electrode and second conductive spacers on the cathode layer of the second substrate.Type: ApplicationFiled: February 29, 2024Publication date: June 20, 2024Inventors: Xiangyong KONG, Dongfang WANG