Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.

Abstract: Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.

Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.

Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.

Abstract: The invention comprises a system and method for testing a component, wherein the component comprises a plurality of elements. The invention comprises a tester that subjects the plurality of elements to a plurality of tests, wherein the plurality of tests has a criteria, each test of the plurality of tests has the criteria at a value, and each value is different for each test. The invention comprises a plotter that receives a plurality of results from the plurality of tests and forms a bit map comprising a plurality of sections, wherein each section depicts at least a portion of the component and locations for any failing elements within the portion, and each section represents the result of a test of the plurality of tests.

Abstract: The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.

Abstract: The inventive control logic provides the selection signals for a bi-endian rotator MUX. The logic determines the starting point for the data transfer by determining which input register byte is going to Byte 0 of the output register. The control logic passes the starting point to single decoder. The decoded value is then sent to a plurality of MUXs, one for each of the output register bytes. Each of the MUXs is prewired to receive a portion of bits of the decoded value, and the portion is arranged in a particular order. The MUXs then send their respective outputs to the rotator MUX as selection control signals.

Abstract: A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state. A second anti-fuse has a programmed state and an unprogrammed state and couples the first node to a second power supply when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state. The state of the programmed signal can be used to replace a primary circuit element of an integrated circuit with a redundant circuit element.

Abstract: The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.

Abstract: An electronically programmed mask is connected to an electronic device, such as a processor. In operation, a mask design is first entered into the processor. The processor controls a display of an image on the electronically programmed mask, wherein the display replicates conventional type masks. The electronically programmed mask is designed such that the display presented on its screen provides optical contrast and characteristics that are easily changed or reprogrammed by the processor. Electronically controlled masks provide the same patterns as mechanical type masks without requiring rigid, permanent type structures to form a desired pattern.

Abstract: An electronically programmed mask is connected to an electronic device, such as a processor. In operation, a mask design is first entered into the processor. The processor controls a display of an image on the electronically programmed mask, wherein the display replicates conventional type masks. The electronically programmed mask is designed such that the display presented on its screen provides optical contrast and characteristics that are easily changed or reprogrammed by the processor. Electronically controlled masks provide the same patterns as mechanical type masks without requiring rigid, permanent type structures to form a desired pattern.

Abstract: A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field oxide layer. In a further embodiment, the polysilicon layer comprises a bottom conductor layer in the antifuse. In another embodiment, a refractory metal silicide layer is formed between the polysilicon layer and the antifuse. In yet a further embodiment, the refractory metal silicide layer comprises the bottom conductor layer in the antifuse.

Abstract: The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.

Abstract: Disclosed are methods and apparatus for finding an element meeting a predetermined condition among an ordered set of N elements. The method subdivides the ordered set of N elements into M subsets, wherein 1<M<N. A particular one of the M subsets contains K elements. The method determines if the particular subset contains an element meeting the predetermined condition. The method also identifies which of the K elements in the particular subset is the first element meeting the predetermined condition.

Abstract: Circuitry for detecting snoop hits during the propagation and storage delay when transmitting a victim address to a bus cluster in a multiprocessor system. The circuitry includes stages for detecting the snoop hits during each cycle of the propagation delay. Each stage includes logic gates for comparing the wordline address with a snoop hit and for outputting a snoop hit signal upon detection of a snoop hit relating to the snoop address.

Abstract: A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state. A second anti-fuse has a programmed state and an unprogrammed state and couples the first node to a second power supply when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state. The state of the programmed signal can be used to replace a primary circuit element of an integrated circuit with a redundant circuit element.

Abstract: A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state. A second anti-fuse has a programmed state and an unprogrammed state and couples the first node to a second power supply when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state. The state of the programmed signal can be used to replace a primary circuit element of an integrated circuit with a redundant circuit element.

Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.

Abstract: A cache with a translation lookaside buffer (TLB) that reduces the time required for retrieval of a physical address from the TLB when accessing the cache in a system that supports variable page sizing. The TLB includes a content addressable memory (CAM) containing the virtual page numbers corresponding to pages in the cache and a random access memory (RAM) storing the physical page numbers of the pages corresponding to the virtual page numbers in the CAM. The physical page number RAM stores a page mask along with the physical page numbers, and includes local multiplexers which perform virtual address bypassing of the physical page number when the page has been masked.

Abstract: A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field oxide layer. In a further embodiment, the polysilicon layer comprises a bottom conductor layer in the antifuse. In another embodiment, a refractory metal silicide layer is formed between the polysilicon layer and the antifuse. In yet a further embodiment, the refractory metal silicide layer comprises the bottom conductor layer in the antifuse.