Patents by Inventor Duck-Ju Kim
Duck-Ju Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8199583Abstract: A method of performing a read operation in a flash memory device is disclosed. The flash memory has a memory cell array including at least one block, the block having a plurality of pages. The method comprises receiving a read command to read data from a selected page in the block; determining whether or not the block has any page that has not been programmed; performing a dummy data program operation on at least one page that is determined not to have been programmed; and executing the read command to read the data of the selected page after the dummy data program operation is completed.Type: GrantFiled: February 8, 2010Date of Patent: June 12, 2012Assignee: Hynix Semiconductor Inc.Inventors: You Sung Kim, Duck Ju Kim
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Patent number: 8107291Abstract: A method of programming data in a flash memory device is disclosed. The memory device includes a memory cell array which in turn includes at least one block, and the block in turn includes a plurality of pages. A program command to program a plurality of pages in the block is received. The plurality of pages is programmed in a predefined order. An address corresponding to a page that was programmed last amongst the plurality of pages is stored.Type: GrantFiled: February 8, 2010Date of Patent: January 31, 2012Assignee: Hynix Semiconductor Inc.Inventors: You Sung Kim, Duck Ju Kim
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Patent number: 8102717Abstract: A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, supplying a second voltage to the second bit line, floating the second bit line and evaluating the second bit line for a set time period, and detecting a voltage level of the second bit line and outputting a test result of testing for the leakage current between the first and second bit lines by the page buffer.Type: GrantFiled: December 30, 2009Date of Patent: January 24, 2012Assignee: Hynix Semiconductor Inc.Inventors: Jae Won Cha, Duck Ju Kim
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Publication number: 20120008397Abstract: A memory system includes a flash memory device including a first memory block group on which a least significant bit (LSB) program operation has been performed and a program operation on another bit has not been performed and a second memory block group on which both the LSB program operation and a most significant bit (MSB) program operation have been performed and a memory controller configured to check which of the first and second memory block groups a memory block selected for an LSB data read operation belongs to and set a level of a read voltage for the LSB data read operation of the selected memory block.Type: ApplicationFiled: July 8, 2011Publication date: January 12, 2012Inventors: Tai Sik SHIN, Duck Ju KIM, Dong Hyeon HAM
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Patent number: 8068368Abstract: A method of performing a read operation in a flash memory device is disclosed. The flash memory has a memory cell array including at least one block, the block having a plurality of pages. The method comprises receiving a read command to read data from a selected page in the block; determining whether or not the block has any page that has not been programmed; performing a dummy data program operation on at least one page that is determined not to have been programmed; and executing the read command to read the data of the selected page after the dummy data program operation is completed.Type: GrantFiled: February 8, 2010Date of Patent: November 29, 2011Assignee: Hynix Semiconductor Inc.Inventors: You Sung Kim, Duck Ju Kim
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Patent number: 8045393Abstract: According to an aspect of a program method of a nonvolatile memory device, a first program operation for programming a first data stored in a first latch may be performed and a cache program signal may be input for inputting a second data to be programmed subsequently. When the cache program signal is input, a determination is made as to whether a first program verify operation is being performed, and if so, the verify operation is stopped, the second data is input, and the first program verify operation is restarted.Type: GrantFiled: December 31, 2008Date of Patent: October 25, 2011Assignee: Hynix Semiconductor Inc.Inventors: Byung Ryul Kim, Jun Seop Chung, Duck Ju Kim
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Patent number: 8036037Abstract: A method of programming data in a flash memory device is disclosed. The memory device includes a memory cell array which in turn includes at least one block, and the block in turn includes a plurality of pages. A program command to program a plurality of pages in the block is received. The plurality of pages is programmed in a predefined order. An address corresponding to a page that was programmed last amongst the plurality of pages is stored.Type: GrantFiled: February 8, 2010Date of Patent: October 11, 2011Assignee: Hynix Semiconductor Inc.Inventors: You Sung Kim, Duck Ju Kim
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Patent number: 8036042Abstract: A method of operating a nonvolatile memory device includes performing a reset operation for setting a level of a program voltage to a first level, performing a program operation and a verification operation on memory cells included in a first page of a first memory block while raising the program voltage from the first level, storing a level of the program voltage, supplied to the first page when memory cells programmed to have threshold voltages with at least a verification voltage are detected during the verification operation, as a second level, while raising the program voltage from the second level, performing the program operation and the verification operation on each of second to last pages of the first memory block, and after completing the program operation for the first memory block, performing the reset operation for setting the level of the program voltage to the first level.Type: GrantFiled: December 31, 2009Date of Patent: October 11, 2011Assignee: Hynix Semiconductor Inc.Inventors: Byung Ryul Kim, Duck Ju Kim, You Sung Kim, Se Chun Park
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Patent number: 8004914Abstract: A method includes performing test bit setting; programming a first page using data set by the test bit setting, and storing a fail status bit in a page buffer, which is connected to a first bit line having a fail status, based on a verification result of the test program; performing a test program and verification on a second page based on a test program and fail status bit storage result of a preceding page, and storing a fail status bit in the page buffer, which is connected to a second bit line having a fail status, based on a verification result of the test program and verification; and after a test program, verification, and fail status bit setting with respect to the entire pages of a memory block are completed, outputting data of the page buffer.Type: GrantFiled: March 9, 2009Date of Patent: August 23, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae Won Cha, Duck Ju Kim
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Patent number: 7903466Abstract: A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array.Type: GrantFiled: December 28, 2007Date of Patent: March 8, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jong Hyun Wang, Duck Ju Kim, Seong Hun Park, Chang Won Yang
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Publication number: 20100302881Abstract: A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level determination signal having a varying data value in response to a selection signal, and a voltage generation unit configured to generate a voltage having a single pulse form or a voltage having a pulse form whose rising edge portion rises in incremental voltage steps in response to the voltage level determination signal outputted from the voltage generation control unit.Type: ApplicationFiled: December 31, 2009Publication date: December 2, 2010Inventors: Byung Ryul KIM, Duck Ju Kim, You Sung Kim, Se Chun Park
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Publication number: 20100302866Abstract: A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, supplying a second voltage to the second bit line, floating the second bit line and evaluating the second bit line for a set time period, and detecting a voltage level of the second bit line and outputting a test result of testing for the leakage current between the first and second bit lines by the page buffer.Type: ApplicationFiled: December 30, 2009Publication date: December 2, 2010Inventors: Jae Won CHA, Duck Ju Kim
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Publication number: 20100302864Abstract: A method of operating a nonvolatile memory device includes performing a reset operation for setting a level of a program voltage to a first level, performing a program operation and a verification operation on memory cells included in a first page of a first memory block while raising the program voltage from the first level, storing a level of the program voltage, supplied to the first page when memory cells programmed to have threshold voltages with at least a verification voltage are detected during the verification operation, as a second level, while raising the program voltage from the second level, performing the program operation and the verification operation on each of second to last pages of the first memory block, and after completing the program operation for the first memory block, performing the reset operation for setting the level of the program voltage to the first level.Type: ApplicationFiled: December 31, 2009Publication date: December 2, 2010Inventors: Byung Ryul KIM, Duck Ju Kim, You Sung Kim, Se Chun Park
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Patent number: 7830180Abstract: A noise protector includes a first noise control block for NORing an input signal and a first trimmed input signal and providing an output; a second noise control block for NANDing the input signal and a second trimmed input signal and providing an output; and an output signal generation block for outputting an output signal removed of noise in response to the outputs of the first noise control block and the second noise control block.Type: GrantFiled: May 8, 2008Date of Patent: November 9, 2010Assignee: Hynix Semiconductor Inc.Inventors: Byoung Sung You, Duck Ju Kim
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Patent number: 7796434Abstract: Program voltages of a non-volatile memory device are controlled variably according to a program/erase operation count. The non-volatile memory device includes a program voltage supply unit for applying a program voltage to a memory cell, a program/erase count storage unit for storing a total program/erase operation count of the non-volatile memory device, a program start voltage storage unit for storing levels of program start voltages to be differently supplied according to the program/erase operation count, and a program voltage controller for controlling the program start voltage according to the program/erase operation count.Type: GrantFiled: March 14, 2008Date of Patent: September 14, 2010Assignee: Hynix Semiconductor Inc.Inventors: Chae Kyu Jang, Joong Seob Yang, Duck Ju Kim, Jong Hyun Wang, Seong Hun Park
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Patent number: 7782676Abstract: A method of operating a nonvolatile memory device includes floating a drain select line, a source select line, a well, and a common source line of the nonvolatile memory device; precharging a program-inhibited bit line; and performing a program operation by applying a program voltage to a selected word line. The select lines and the well are floated to prevent the influence of a voltage applied to a bit line. Accordingly, degradation of the nonvolatile memory device can be prevented.Type: GrantFiled: June 28, 2008Date of Patent: August 24, 2010Assignee: Hynix Semiconductor Inc.Inventors: Jae Won Cha, Duck Ju Kim
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Patent number: 7778096Abstract: A bad block address of a flash memory device is stored through a fuse circuit and then compared with an input address in order to disable bad blocks. The flash memory device includes a bad block information unit for storing an address of a bad block, a comparator for comparing an input address including a memory block address and the address of the bad block stored in the bad block information unit, and for outputting a first control signal according to the comparison result, and an address counter for outputting a second control signal to enable or disable a memory block corresponding to the memory block address in response to the first control signal.Type: GrantFiled: May 12, 2008Date of Patent: August 17, 2010Assignee: Hynix Semiconductor Inc.Inventors: You Sung Kim, Duck Ju Kim
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Publication number: 20100142282Abstract: A method of programming data in a flash memory device is disclosed. The memory device includes a memory cell array which in turn includes at least one block, and the block in turn includes a plurality of pages. A program command to program a plurality of pages in the block is received. The plurality of pages is programmed in a predefined order. An address corresponding to a page that was programmed last amongst the plurality of pages is stored.Type: ApplicationFiled: February 8, 2010Publication date: June 10, 2010Applicant: Hynix Semiconductor Inc.Inventors: You Sung KIM, Duck Ju KIM
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Publication number: 20100135076Abstract: A method of performing a read operation in a flash memory device is disclosed. The flash memory has a memory cell array including at least one block, the block having a plurality of pages. The method comprises receiving a read command to read data from a selected page in the block; determining whether or not the block has any page that has not been programmed; performing a dummy data program operation on at least one page that is determined not to have been programmed; and executing the read command to read the data of the selected page after the dummy data program operation is completed.Type: ApplicationFiled: February 8, 2010Publication date: June 3, 2010Applicant: Hynix Semiconductor Inc.Inventors: You Sung Kim, Duck Ju Kim
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Publication number: 20100135077Abstract: A method of performing a read operation in a flash memory device is disclosed. The flash memory has a memory cell array including at least one block, the block having a plurality of pages. The method comprises receiving a read command to read data from a selected page in the block; determining whether or not the block has any page that has not been programmed; performing a dummy data program operation on at least one page that is determined not to have been programmed; and executing the read command to read the data of the selected page after the dummy data program operation is completed.Type: ApplicationFiled: February 8, 2010Publication date: June 3, 2010Applicant: Hynix Semiconductor Inc.Inventors: You Sung KIM, Duck Ju Kim