Abstract: A reference circuit in a ferroelectric memory includes a reference plate line and a reference word line adjacently formed in a first direction in correspondence with a cell block including a plurality of unit cells; a plurality of bit lines connected to the unit cells and formed in a second direction; a plurality of parallelly disposed reference capacitors each having a first electrode connected to the reference plate line and a second electrode connected to a storage node SN of a reference cell; an initializing unit connected to the storage node for initializing a level of the reference cell; and a switching block formed between the bit lines and the storage node in correspondence with the bit lines and controlled by signals applied to the reference word line.

Abstract: A ferroelectric memory device includes a cell array block having a plurality of sub-cell array blocks regularly arranged in columns and rows, each sub-cell array block includes a plurality of unit cells, a plurality of main bitlines disposed along a first direction corresponding to the sub-cell array blocks in column units, a plurality of sub-bitlines disposed along the first direction in a one-to-one correspondence to the sub-cell array blocks, a plurality of pairs of sub-bitline pull down signal application lines and sub-bitline enable switch signal application lines disposed along a second direction perpendicular to the first direction, each pair corresponding to the sub-cell array block for applying a sub-bitline enable switch signal and a sub-bitline pull down signal, and a plurality of switching control blocks, each corresponding to the sub-cell array block for one of enabling the sub-bitlines selectively in response to the sub-bitline enable switch signal and pulling down the sub-bitlines in response t

Abstract: A circuit for testing a ferroelectric capacitor in a ferroelectric random access memory (FRAM) for storing a data at the ferroelectric capacitor includes a test pulse signal generating part for generating a test pulse signal for measuring variation of charge in the ferroelectric capacitor, a test pulse providing part for digitizing the test pulse signal by using a reference voltage signal to provide a digital test pulse signal, an n-bit counter for making a 2n clock counting per a cycle in response to the digital test pulse signal as a clock signal, a measuring control signal providing part for subjecting count outputs for each bit, and the digital test pulse signal to logic operation, to provide a measuring control signal, a write pulse bar signal generating part for generating a write pulse bar signal in correspondence to a specific bit count output within a specific period, an input drive control part for receiving the reference voltage signal, a voltage signal at the first electrode of the ferroelectric c

Abstract: A fail repair circuit of a nonvolatile ferroelectric memory device and a method for repairing the same are disclosed, in which a redundancy time can be reduced and a redundancy algorithm can be changed or added at any time.

Abstract: A column repair circuit and method of a nonvolatile ferroelectric memory device can include: a memory test logic block capable of generating a redundancy active pulse (RAP) and a corresponding fail input/output(IO) number FION<r> if a column address including a fail bit to be repaired is found during test; a power-up sensor capable of generating a power-up pulse if a stable power source voltage is sensed; a first redundancy control block capable of generating first to fifth control signals ENN, ENP, EQN, CPL, and PREC and a sixth control signal ENW in response to the RAP and the power-up pulse; a counter generating n bit counter bit signal increased by one bit through the RAP to correspond to the number of redundancy bits; a redundancy counter decoding control block capable of generating an activated coding signal ENW<n> in response to the counter bit signal of the counter and the sixth control signal ENW; and a redundancy coding block capable of coding a fail column address in response to the cod

Abstract: A boost voltage generating circuit and method for a nonvolatile ferroelectric memory device is disclosed in the present invention. The present invention provides a stable operation when a power source supply voltage region is in a wide power source voltage region, and a layout area for generating a boost voltage is reduced, thereby reducing a chip cost.

Abstract: A boost voltage generating circuit and method for a nonvolatile ferroelectric memory device is disclosed in the present invention. The present invention provides a stable operation when a power source supply voltage region is in a wide power source voltage region, and a layout area for generating a boost voltage is reduced, thereby reducing a chip cost.

Abstract: A method for driving a nonvolatile ferroelectric memory device enabling an operation of a writing mode and a reading mode of a data to be carried out equally in an entire cell array and being suitable for reducing cell size by decreasing a minimum sensing voltage is disclosed.

Abstract: A nonvolatile ferroelectric memory device and method for driving the same includes data reading and writing operations performed uniformly in a whole cell array and reduces the size of a cell by lowering a sensing voltage. The nonvolatile ferroelectric memory device includes a main cell and a reference cell provided with one transistor and one or more ferroelectric capacitors among a first voltage applying line (wordline), a bitline and a second voltage applying line.

Abstract: A method for driving a nonvolatile ferroelectric memory device enabling an operation of a writing mode and a reading mode of a data to be carried out equally in an entire cell array and being suitable for reducing cell size by decreasing a minimum sensing voltage is disclosed.

Abstract: In a circuit for generating timing of a reference plate line in the nonvolatile ferroelectric memory device, wherein a nonvolatile ferroelectric memory device having a reference cell includes a switching block controlled by a reference wordline signal, a level initiating block which selectively initiates a level of an input terminal of the switching block after receiving a reference equalizer signal, and a plurality of ferroelectric capacitors connected in parallel between the input terminal of the switching block and the reference plate line, the circuit includes a latch circuit receiving a first signal which has the same waveform as that of a chip enable signal and is not delayed and a second signal which has the same waveform as that of the chip enable signal and is delayed for a first period as the chip enable signal is generated, so as to output a low signal only in a delayed period of the second signal, and a delay circuit delaying the first and second signals of the latch circuit to output a low signal

Abstract: A nonvolatile ferroelectric memory device and method for driving the same includes data reading and writing operations performed uniformly in a whole cell array and reduces the size of a cell by lowering a sensing voltage. The nonvolatile ferroelectric memory device includes a main cell and a reference cell provided with one transistor and one or more ferroelectric capacitors among a first voltage applying line (wordline), a bitline and a second voltage applying line.

Abstract: The present invention relates to a cell structure of a ferroelectric memory device which can prevent a data loss and improve a data read/write speed, including: first and second MOS transistors connected in series between two bit lines, and performing a switching operation according to an enable state of a word line; a third MOS transistor connected between the first and second MOS transistors and a plate line, and engaged with the first and second MOS transistors according to an enable state the word line; and first and second ferroelectric capacitors connected between the first MOS transistor and the third MOS transistor, and between the second MOS transistor and the third MOS transistor, respectively, and storing data in accordance with a switching state of the first to third MOS transistors. Accordingly, the present invention can carry out a high-speed data sensing operation and a restoring operation, and can prevent the data from being lost, which results in improved speed and reliability.

Abstract: An apparatus for generating a reference voltage in ferroelectric memory device including a sense amplifier which senses and amplifies a voltage difference between a bit line and a bit line bar, and a plurality of memory cells, each having a ferroelectric capacitor, includes a linear capacitor, in response to a predetermined voltage signal inputted from a cell plate line, for storing a predetermined amount of charges; a first switching device for selectively coupling the linear capacitor to the cell plate line; a second switching device for selectively coupling the linear capacitor to the bit line to thereby provide the predetermined amount of charges as the reference voltage to the bit line.

Abstract: A semiconductor memory device, includes: a single bit line; at least one memory cell coupled to said single bit line for storing a first charge corresponding to predetermined data; a reference voltage generation circuit for generating a reference voltage as a first voltage; a charge pump circuit for generating a second charge substantially corresponding to the reference voltage; a transistor for combining the first charge with the second charge at a read operation, thereby generating a second voltage; and a sense amplifier coupled to said single bit line for sensing and amplifying a difference between the first voltage and the second voltage, to thereby read out the predetermined data. The semiconductor memory device can reduce its chip size by employing the single bit line coupled to at least one memory cell and effectively sense and amplify the difference between the first voltage from the reference voltage generation circuit and the second voltage from the single bit line at the read operation.

Abstract: There is provided a redundancy circuit of a ferroelectric memory device capable of performing a repair software-wise, the redundancy circuit of a ferroelectric semiconductor device having an address buffer, a normal decoder, a normal memory cell array and a redundancy circuit, said redundancy circuit comprises: a redundancy memory cell array; a first programming unit for storing a fail address signal; a second programming unit for storing a fail number signal; a controller for generating control signals which control the first programming unit and the second programming unit; an address comparator for comparing the fail address stored in the first programming unit with the address of the address buffer; and a redundancy decoder for activating the normal memory cell array or the redundancy memory cell array, according to the address of the address buffer, the output signal of the address comparator and the output signal of the second programming unit. Also, a redundancy method is disclosed.