Abstract: A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.

Abstract: A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded.

Abstract: A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier

Abstract: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

Abstract: Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, programming a plurality of cells with programming pulses without discharging a global bit line carrying a programming voltage between programming pulses, and programming a cell with transient currents.

Abstract: A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded.

Abstract: A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.

Abstract: A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.

Abstract: A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded.

Abstract: Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, programming a plurality of cells with programming pulses without discharging a global bit line carrying a programming voltage between programming pulses, and programming a cell with transient currents.

Abstract: A non-volatile device and method of operating the device including changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step may include determining a history read reference level of a history cell associated with a group of memory cells of a non-volatile memory cell array and comparing sensed logical state distributions with stored logical state distributions.

Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.

Abstract: A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded.

Abstract: A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level for correct reading of at least one history cell, selecting a memory read reference level according to the first read reference level, and reading non-volatile memory array cells associated with the at least one history cell using the memory read reference level.

Abstract: A capacitor including a first active layer capacitively coupled to a second active layer, the second active layer being capacitively coupled to a third layer, the third layer being capacitively coupled to a fourth layer, wherein an anode of the capacitor is connected to one of the first and second active layers, and a cathode of the capacitor is connected to the other one of the first and second active layers, and wherein the third layer is left floating. The fourth layer may be connected to a supply voltage, such as but not limited to, ground.

Abstract: A memory circuit arrangement includes a memory cell array having a plurality of memory cells. A memory read/verify control circuit controls a read operation and/or a verify operation on one or a plurality of memory cells of the memory cell array. The memory read/verify control circuit is adapted to read and/or verify the status of each memory cell of the memory cell array according to read and/or verify instruction information on memory cell level.

Abstract: A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier

Abstract: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

Abstract: The present invention consists of a method and system for compensating, over time and over an operating temperature range, for margin loss in a non-volatile memory (“NVM”) cell, which method comprises selection of a reference level based on temperature readings obtained from a temperature sensing element that is thermally coupled, directly or indirectly, to the NVM cell. The reference level may be selected from a group consisting of references levels of various types, or it may be obtained by adjusting the output of a single reference based on the temperature reading(s), or it may be obtained by utilizing pre-stored conversion data, which conversion data associates a given temperature reading with a corresponding temperature range that is, in turn, associated with a corresponding reference level. A pool of likewise reference cells may be provided, and the reference level may be selected from this pool, based on its association to the temperature reading.

Abstract: A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.