Abstract: A NOR array includes a first plurality of word lines, a second plurality of bit lines and a third plurality of common lines. Each word line connects to the gates of a row of nitride read only memory (NROM) cells. Each bit line connects to one diffusion area of each NROM cell in a column of the NROM cells and each common line connects to the other diffusion areas of each NROM cell in a row of the NROM cells.

Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is onboard the die containing the memory array, but not a cell within the memory array.

Abstract: A charge pump regulator for providing a constant boosted voltage at the output of a charge pump includes: 1) a charge pump; 2) a clamping regulator; and 3) a clamping transistor. Certain preferred embodiments further include an auxiliary charge pump that provides a voltage above VDD or below ground to the clamping regulator. The clamping transistor provides a voltage supply level (Vsupp) to the oscillating clock signal generator which uses Vsupp to drive the oscillating clock signals that charge the energy injection capacitors of the charge pump between Vsupp and a reference voltage (Vref). The invention includes regulators for use with positive and negative charge pumps.

Abstract: A circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (Vct) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control tern connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as Vct.

Abstract: A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.

Abstract: An architecture and method for implementing a non-strobed operation on an array cell within a memory array in which a reference unit is provided for emulating the response of an array cell during a desired operation, for example, a read, program verify, erase verify or other types of read operations. The reference unit includes a reference cell which is driven by a non-strobed gate voltage. The architecture and method permit relatively noise-free array cell interrogations at close to ground voltage levels.

Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of the selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.

Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array, the method including refreshing a threshold voltage of a bit of a memory cell in an EEPROM array, the threshold voltage being different than a previous threshold voltage, by restoring the threshold voltage of the bit at least partially back to the previous threshold voltage.

Abstract: A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until the threshold voltage level is above a final target level.

Abstract: A charge pump regulator for providing a constant boosted voltage at the output of a charge pump includes: 1) a charge pump; 2) a clamping regulator; and 3) a clamping transistor. Certain preferred embodiments further include an auxiliary charge pump that provides a voltage above VDD or below ground to the clamping regulator. The clamping transistor provides a voltage supply level (Vsupp) to the oscillating clock signal generator which uses Vsupp to drive the oscillating clock signals that charge the energy injection capacitors of the charge pump between Vsupp and a reference voltage (Vref). The invention includes regulators for use with positive and negative charge pumps.

Abstract: A method for operating a charge pump, the method including biasing a bulk of a charge pump stage so as to reduce body effect without forward biasing diodes of the charge pump stage.

Abstract: An architecture and method for implementing a non-strobed operation on an array cell within a memory array in which a reference unit is provided for emulating the response of an array cell during a desired operation, for example, a read, program verify, erase verify or other types of read operations. The reference unit includes a reference cell which is driven by a non-strobed gate voltage. The architecture and method permit relatively noise-free array cell interrogations at close to ground voltage levels.

Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is onboard the die containing the memory array, but not a cell within the memory array.

Abstract: A multi-stage charge pump apparatus and a method for powering and controlling the same is presented. Each stage of the charge pump includes an energy injection capacitor and a gate control capacitor to permit the transfer and accumulation of charge through the charge pump to an output through the use of transistor switches. The charge pump is driven by a pair of clock signals where the voltage swing of the clock signal driving the control gate capacitors is advantageously set to a higher level than that of the clock signal driving the energy injection capacitor. In this manner, the effect of bulk voltages in the later stages of the charge pump is overcome.

Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of the selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.

Abstract: A regulator circuit to deliver a regulated boosted voltage VPP from a charge pump to electrodes of the cells of a non-volatile memory (NVM) array, such as an EPROM, integrated circuit device. The regulator includes a differential amplifier operating from a VDD voltage lower than VPP that drives a gain stage whose output is to a current mirror operating from the boosted VPP voltage. The current mirror output is taken across a voltage divider as the regulated output of the circuit. The differential amplifier has one input at a fixed voltage and the other being a feedback voltage from the voltage divider to control the gain of the differential amplifier and thereby regulate the output of the gain stage and current mirror in response to a variable load current of the integrated circuit device.

Abstract: A symmetric, segmented array includes select transistors and a regulated voltage supply. At least one select transistor is connected to each diffusion bit line. The regulated voltage supply is connected to the gates of the select transistors. The regulated voltage defines the voltage that the selected transistors provide to the diffusion bit lines. Alternatively, the array includes transistors connected to the metal bit lines and a regulated voltage supply connected to the gates of the transistors. The regulated voltage defines the voltage that the transistors provide to the metal bit lines.

Abstract: A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed of a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steeps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.

Abstract: A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until the threshold voltage level is above a final target level.

Abstract: A memory array includes a first plurality of metal bit lines, a second plurality of diffusion bit lines and a third plurality of select transistors. There are more than two diffusion bit lines per metal bit line.