Abstract: A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer.

Abstract: A spacer structure for FinFETs. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.

Abstract: A method for configuring J electromagnetic radiation sources (J?2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2; J?I) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. in each of I independent exposure steps, the I stacks are concurrently exposed to radiation from the J sources, Vi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i in exposure step i (i=1, . . . , I). t(i) and Pt(i) are computed such that: Vi is maximal through deployment of source t(i) as compared with deployment of any other source for i=1, . . . , I; and an error E being a function of |V1?S1|, |V2?S2|, . . . , |Vi?Si| is about minimized with respect to Pi (i=1, . . . , I).

Abstract: A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer.

Abstract: A structure formation method. First, a structure is provided including (a) a fin region comprising (i) a first source/drain portion having a first surface and a third surface parallel to each other, not coplanar, and both exposed to a surrounding ambient, (ii) a second source/drain portion having a second surface and a fourth surface parallel to each other, not coplanar, and both exposed to the surrounding ambient, and (iii) a channel region disposed between the first and second source/drain portions, (b) a gate dielectric layer, and (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region. Next, a patterned covering layer is used to cover the first and second surfaces but not the third and fourth surfaces. Then, the first and second source/drain portions are etched at the third and fourth surfaces, respectively.

Abstract: A semiconductor structure. The structure includes (a) a fin region having (i) a first source/drain portion having a first surface and a third surface, wherein the first and third surfaces are (A) parallel to each other and (B) not coplanar, (ii) a second source/drain portion having a second surface and a fourth surface, wherein the second and fourth surfaces are (A) parallel to each other and (B) not coplanar, and (iii) a channel region; (b) a gate dielectric layer; (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region; and (d) first second strain creating regions on the third and fourth surfaces, respectively, wherein the first and second strain creating regions comprise a strain creating material.

Abstract: A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.

Abstract: A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

Abstract: A method for forming a semiconductor structure. The method includes providing a semiconductor structure including a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) a semiconductor body region. The method further includes implanting an adjustment dose of dopants of a first doping polarity into the semiconductor body region by an adjustment implantation process. Ion bombardment of the adjustment implantation process is in the reference direction. The method further includes (i) patterning the semiconductor substrate resulting in side walls of the semiconductor body region being exposed to a surrounding ambient and then (ii) implanting a base dose of dopants of a second doping polarity into the semiconductor body region by a base implantation process. Ion bombardment of the base implantation process is in a direction which makes a non-zero angle with the reference direction.

Abstract: A memory cell (e.g., static random access memory (SRAM) cell) includes a plurality of back-gated n-type field effect transistors (nFETs), and a plurality of double-gated p-type field effect transistors (pFETs) operatively coupled to the plurality of nFETs.

Abstract: A method for forming a semiconductor transistor with an expanded top portion of a gate The gate is expanded through implanting atoms in the top portion of transistor's gate electrode region. The transistor formed includes a semiconductor region having two source/drain regions and a gate dielectric region formed on the channel region between the source/drain regions. The gate electrode region is formed on the gate dielectric region. The gate electrode region is formed such that it is electrically insulated from the channel region by the gate dielectric region. The top of the gate electrode region formed is wider than the bottom of the gate electrode region.

Abstract: A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region.

Abstract: An anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two signals meet a predetermined failure criteria, for example, equivalent rising edges. The disrupt signal causes a signal gate or similar element within the counterfeited IC to fail, disrupt, or in some way change a designed behavior of the IC. The disrupt signal may be reset so that the failure will occur again when predetermined failure criteria are met. The authentic IC functions according to design because at least one of the elements in the anti-counterfeit circuit is a camouflage circuit, thus, in an authentic IC the anti-counterfeit circuit is not operatively coupled.

Abstract: A verification system disclosed herein uses the unique signatures of an IC to perform authentication of the IC after the IC is shipped to a customer. The verification system records the fingerprint and associated IC identifier with the fingerprint into a data structure. The data structure is supplied to the customer for use in the customer's own security systems. When an IC interfaces with the customer's system, the verification system requests the IC's identifier and selects a data structure corresponding to that IC identifier. The verification system then performs a test on the IC (e.g. remotely operates the IC at 1V), records the resulting data and compares the test results with the corresponding data in the data structure. If a predetermined condition is satisfied then the IC is verified to be authentic. If not, the verification system responds, for example, by flagging the customer's security system.

Abstract: A design structure for an anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two signals meet a predetermined failure criteria, for example, equivalent rising edges. The disrupt signal causes a signal gate or similar element within the counterfeited IC to fail, disrupt, or in some way change a designed behavior of the IC. The disrupt signal may be reset so that the failure will occur again when predetermined failure criteria are met. The authentic IC functions according to design because at least one of the elements in the anti-counterfeit circuit is a camouflage circuit, thus, in an authentic IC the anti-counterfeit circuit is not operatively coupled.

Abstract: An article of manufacture, for example, a product or portion of a product produced by an IP design house which, when manufactured, causes random failures in a counterfeit integrated circuit. The article of manufacture (520) is a “genetic code” that comprises all of the necessary functional information needed to build an electronic circuit. This article of manufacture, when processed in a computer-aided design system and/or a fabrication facility, generates a functional apparatus such as an anti-counterfeiting circuit.

Abstract: A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.

Abstract: A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

Abstract: A spacer structure for FinFETs. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.

Abstract: A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.