Patents by Inventor Effendi Leobandung

Effendi Leobandung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10304947
    Abstract: A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung
  • Patent number: 10304839
    Abstract: A metal strap is formed in a middle-of-line (MOL) process for communication between an eDRAM and a FinFET. An oxide is deposited in a trench over the eDRAM to prevent development of an epitaxial film prior to formation of the metal strap. The result is an epiless eDRAM strap in a FinFET.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10303998
    Abstract: A floating gate setup method, system, and computer program product include, in an initial setup of weights for a floating gate including rows, columns, and a separate input line: comparing a current weight to a desired weight, performing a feedback to the input line to set a voltage to change the floating gate FET VT and the current weight, and checking that the current weight is within a predetermined tolerance of the desired weight.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Publication number: 20190157845
    Abstract: A method of forming a pair of edge-emitting lasers is provided. The method includes forming a mesa from a substrate, forming a cover layer on the substrate around the mesa, and forming a first barrier layer on each of opposite sidewalls of the mesa. The method further includes forming a quantum well layer on each of the barrier layers, forming a second barrier layer on each of the quantum well layers, and forming a cladding layer on each of the second barrier layers.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 23, 2019
    Inventors: Effendi Leobandung, Ning Li, Tak H. Ning
  • Publication number: 20190157158
    Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a plurality of semiconductor fins patterned in a starting semiconductor substrate; a set of gate structures formed on the starting semiconductor substrate; a set of spacers formed around each of the set of gate structures; a source and drain region grown around the plurality of fins; a conductive metal material on the source and drain region, an insulating material is configured to be deposited over an upper surface of the conductive metal material and the gate structure; and a plurality of contacts in the insulator material. The plurality of contacts is formed such that a bottom surface of the plurality of contacts is in contact with at least a portion of the upper surface of the gate structure.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 23, 2019
    Inventor: Effendi Leobandung
  • Patent number: 10291414
    Abstract: An approach is provided in which an information handling system performs multiple tests on a memory device using different supply voltage levels. The information handling system identifies a set of memory cells in the memory that produce a same result during each of the memory tests at the different supply voltage levels, and generates a unique identifier based on the set of memory cells. In turn, the information handling system uses the unique identifier in one or more processes executed by the information handling system.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Publication number: 20190140424
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10283537
    Abstract: A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ning Li, Devendra K. Sadana
  • Publication number: 20190131304
    Abstract: A semiconductor device includes a source region and a drain region formed in a transistor structure. A channel region is disposed between the source region and the drain region. A cladding layer is formed on the channel region, the cladding layer including a semiconductor material. A gate dielectric of a gate structure is formed on the cladding layer.
    Type: Application
    Filed: October 26, 2017
    Publication date: May 2, 2019
    Inventor: Effendi Leobandung
  • Patent number: 10276685
    Abstract: A structure and method for fabricating a vertical heterojunction tunnel field effect transistor (TFET) using limited lithography steps is disclosed. The fabrication of a second conductivity type source/drain region may utilize a single lithography step to form a first-type source/drain region, and a metal contact thereon, adjacent to a gate stack having a first conductivity type source/drain region on an opposite side.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Publication number: 20190122102
    Abstract: Weights of a neural network are initialized by programming a plurality of unit cells. A given one of the plurality of unit cells includes one or more static random-access memory cells and a digital to analog converter device. The digital to analog converter device is configured to receive one or more outputs produced by respective ones of the one or more static random-access memory cells. An amount of error associated with the initialized weights is determined. The initialized weights are adjusted in response to the amount of error exceeding a threshold amount of error.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 25, 2019
    Inventor: Effendi Leobandung
  • Publication number: 20190123178
    Abstract: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 25, 2019
    Inventors: Effendi Leobandung, Chun-chen Yeh
  • Publication number: 20190123138
    Abstract: A method of forming a nanowire heterostructure, including, forming a dummy nanowire on a substrate, forming a sacrificial cover layer on the dummy nanowire, forming a spacer layer on a portion of the sacrificial cover layer, wherein a portion of the sacrificial cover layer extends above the top surface of the spacer layer, removing the portion of the sacrificial cover layer that extends above the top surface of the spacer layer, forming a gate structure on the spacer layer and a remaining portion of the sacrificial cover layer, forming an interlayer dielectric (ILD) layer on the gate structure, removing the dummy nanowire to form a nanowire trench, and forming a replacement nanowire in the nanowire trench
    Type: Application
    Filed: June 28, 2018
    Publication date: April 25, 2019
    Inventor: Effendi Leobandung
  • Patent number: 10269956
    Abstract: A vertical FET with asymmetrically positioned source region and drain region is provided. The source region of the vertical FET is separated from a gate electrode by a gate dielectric and the drain region of the vertical FET is separated from the gate electrode by a drain spacer formed therebetween.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10269806
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodorus E. Standaert, Xinhui Wang
  • Patent number: 10261067
    Abstract: A nanopore FET sensor device and method of making. The nanopore FET sensor device includes a FET device stack of material layers including a source, channel and drain layers, and a nanoscale hole through the FET device stack to permit flow of strands of molecular material, e.g., DNA, therethrough. The perimeter of the nanoscale hole forms a FET device gate surface. The source and drain layers are provided with respective contacts for connection with measuring instruments that measure a flow of current therebetween. The molecular strands having charged portions pass from one side of a wafer substrate to the other side through the (nanopore) gate and modulate the current flow sensed at the source or drain terminals. The sensor collects real-time measurements of the current flow modulations for use in identifying the type of molecule. Multiple measurements by the same nanopore FET sensor are collected and compared for enhanced detection.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Effendi Leobandung
  • Patent number: 10256319
    Abstract: A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Pranita Kerber, Effendi Leobandung, Philip J. Oldiges
  • Patent number: 10256608
    Abstract: A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiyGe(1-y), where 0.8<y<1, and SizGe(1-z), where 0.2<z<0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of In0.53Ga0.47As having a thickness in a range of about 2 nm to about 5 nm.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 10249632
    Abstract: A method that allows integrating complementary metal oxide semiconductor (CMOS) transistors and a non-volatile memory (NVM) transistor on a single substrate is provided. The NVM transistor includes a gate stack containing a high-k tunneling gate dielectric, a floating gate electrode, a high-k control gate dielectric and a control gate electrode. The high-k tunneling gate dielectric is formed form a first high-k dielectric layer employed in formation of a gate dielectric for a p-type field effect transistor (FET), the floating gate electrode is formed from a capping material layer employed in annealing the first high-k dielectric layer, and the high-k control gate dielectric is formed from a second high-k dielectric layer employed in formation of a gate dielectric for an n-type FET.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10246745
    Abstract: A semiconductor structure is provided that can be used for DNA sequencing detection. The semiconductor structure includes a doped epitaxial source semiconductor material structure located on a first portion of a semiconductor substrate and a doped epitaxial drain semiconductor material structure located on a second portion of the semiconductor substrate. A gate dielectric portion is located on a third portion of the semiconductor substrate and positioned between the doped epitaxial source semiconductor material structure and the doped epitaxial drain semiconductor material structure. A non-stick nucleotide, DNA and DNA polymerase material structure is located atop the doped epitaxial source semiconductor material structure and atop the doped epitaxial drain semiconductor material structure, wherein a cavity is present in the non-stick nucleotide, DNA and DNA polymerase material structure that exposes a topmost surface of the gate dielectric portion.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sanghoon Lee, Effendi Leobandung, Renee T. Mo