Abstract: An approach is provided in which an information handling system performs multiple tests on a memory device using different supply voltage levels. The information handling system identifies a set of memory cells in the memory that produce a same set of results during each of the memory tests at the different supply voltage levels, and generates a random number based on a set of data values collected from the set of memory cells. In turn, the information handling system uses the random number generator in one or more processes executed by the information handling system.

Abstract: Techniques for usage metering by bias temperature instability with differential sensing on pairs of matching transistors are provided. In one aspect, a usage metering device includes: at least one metering circuit on a chip, the at least one metering circuit having a pair of matching transistors, and a differential current sense circuit connected to the pair of matching transistors, wherein the pair of matching transistors includes a reference transistor which is unused during regular operation of the chip, and a stressed transistor that is on continuously during the regular operation of the chip, and wherein the differential current sense circuit determines a Vt difference between the reference transistor and the stressed transistor. A method for usage metering and a method of forming a usage metering device are also provided.

Abstract: According to a first aspect of the present invention, there is provided a method, a computer system and a computer program product. The method, computer system and computer program product including measuring an initial state of a set of SRAM bits on the wafer, identifying a first set of signature SRAM bits on the wafer, of the set of SRAM bits on the wafer, where the first set of SRAM bits comprise a consistent initial state greater than a first threshold percentage of times, measuring physically dimensions of features of the first set of SRAM bits on the wafer; and identifying a set of signature SRAM bits of the first set of SRAM bits on the wafer, wherein the set of signature SRAM bits comprise physical dimensions of features which correlate to the initial state of each correlated SRAM bit.

Abstract: A computer-implemented method executed on a processor for detecting whether a wafer has been tampered during a semiconductor fabrication process, the method including, at a plurality of patterning steps where lithographic patterns are defined and etched or at a plurality of fabrication processing steps, marking, via an identification tool, each die with an unclonable identification in a memory array, inspecting, via an inspection tool, each of the dies, and removing compromised wafers from a wafer pool during the semiconductor fabrication process.

Abstract: Interposer-less multi-chip module are provided. In one aspect, an interposer-less multi-chip module includes: a substrate; a base film disposed on the substrate; and chips pressed into the base film, wherein top surfaces of the chips are coplanar. For instance, the chips can have varying thicknesses and are pressed into the base film to different depths such that top surfaces of the chips are coplanar. An interconnect layer having back-end-of line (BEOL) metal wiring can be present on the wafer over the chips. Methods of forming an interposer-less multi-chip module are also provided.

Abstract: A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised.

Abstract: A method for verifying semiconductor wafers includes receiving a semiconductor wafer including a plurality of layers. A first set of measurement data is obtained for at least one layer of the plurality of layers, where the first set of measurement data includes at least one previously recorded thickness measurement for one or more portions of the at least one layer. The first set of measurement data is compared to a second set of measurement data for the at least one layer. The second set of measurement data includes at least one new thickness measurement for the one or more portions of the at least one layer. The semiconductor wafer is determined to be an authentic wafer based on the second set of measurement data corresponding to the first set of measurement data, otherwise the semiconductor is determined to not be an authentic wafer.

Abstract: A method for semiconductor device fabrication includes forming storage elements on conductive structures. An interlevel dielectric (ILD) layer is formed over the storage elements. Trenches are patterned in the ILD layer to expose a top portion of the storage elements. The storage elements where interlevel vias are to be formed is removed. A conductive material is deposited in the trenches and the via openings to concurrently make contact with the storage elements and form interlevel vias in the via openings.

Abstract: A security key associated with a plurality of programmable switches included in an integrated circuit is received. The plurality of programmable switches are set causing the plurality of programmable switches to be conductive. Reset pulses are applied to a first set of programmable switches included in the plurality of programmable switches based on the received security key.

Abstract: Embodiments of the invention are directed to a transistor that includes a source or drain (S/D) region having an S/D formation assistance region, wherein the S/D formation assistance region includes a top surface, sidewalls, and a bottom surface. The S/D formation assistance region is at least partially within a portion of a substrate. An S/D isolation region is formed around the sidewalls and the bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.

Abstract: A method of forming a field effect transistor (FET) includes providing a substrate; forming an nFET source/drain region on the substrate; forming a pFET source/drain region on the substrate and adjacent to the nFET region, the nFET source/drain region directly contacting the pFET source/drain region; forming a first insulator layer on the nFET source/drain region and the pFET source/drain region; etching away a portion of the first insulator layer between the nFET source/drain region and the pFET source/drain region down to a level of the substrate, thereby breaking the contact between the nFET source/drain region and the pFET source/drain region; and forming a second insulator layer between the nFET source/drain region and the pFET source/drain region in a space formed by the etching, the second insulator layer extending from the substrate to a top of the first insulator layer. The second insulator layer is harder than the first insulator layer.

Abstract: A method can include obtaining a first reference image of a first wafer. The method can include obtaining a first image of the first wafer in a fabrication state. The first wafer can have a first verification structure. The method can include obtaining, when the first wafer is in the fabrication state, a first physical measurement. The first physical measurement can correspond to the first verification structure. The method can include determining that the first image matches the first reference image. The method can include obtaining an electrical parameter measurement corresponding to a verification structure of a received wafer in a post-fabrication state. The method can include calculating a physical parameter value based on the electrical parameter measurement. The method can include generating a verification response by comparing the physical parameter value to the first physical measurement.

Abstract: A method for verifying semiconductor wafers includes receiving a semiconductor wafer including a plurality of layers. A first set of measurement data is obtained for at least one layer of the plurality of layers, where the first set of measurement data includes at least one previously recorded thickness measurement for one or more portions of the at least one layer. The first set of measurement data is compared to a second set of measurement data for the at least one layer. The second set of measurement data includes at least one new thickness measurement for the one or more portions of the at least one layer. The semiconductor wafer is determined to be an authentic wafer based on the second set of measurement data corresponding to the first set of measurement data, otherwise the semiconductor is determined to not be an authentic wafer.

Abstract: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.

Abstract: Weights of a neural network are initialized by programming a plurality of unit cells. A given one of the plurality of unit cells includes one or more static random-access memory cells and a digital to analog converter device. The digital to analog converter device is configured to receive one or more outputs produced by respective ones of the one or more static random-access memory cells. An amount of error associated with the initialized weights is determined. The initialized weights are adjusted in response to the amount of error exceeding a threshold amount of error.

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having an S/D formation assistance region at least partially within a portion of a substrate. An S/D isolation region is formed around sidewalls and a bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.

Abstract: Semiconductor devices and methods of forming the same include forming an etch mask on a stack of alternating dielectric layers and conductor layers. An exposed portion of a dielectric layer and a conductor layer is etched away to form a wordline. The forming and etching steps are repeated, adding additional etch mask material at each iteration, to form respective wordlines at each iteration.

Abstract: A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.

Abstract: Method, systems, crosspoint arrays, and systems for tuning a neural network. A crosspoint array includes: a set of conductive rows, a set of conductive columns intersecting the set of conductive rows to form a plurality of crosspoints, a circuit element coupled to each of the plurality of crosspoints configured to store a weight of the neural network, a voltage source associated with each conductive row, a first integrator attached at the end of at least one of the conductive column, and a first variable resistor attached to the integrator and the end of the at least one conductive column.

Abstract: The wafer comprises a first line in a first layer of the wafer. The first line has a first terminal connected to the first line. The wafer comprises a second line in the first layer of the wafer. The second line has a second terminal connected to the second line. The second terminal has a probe connected to apply a voltage ramp. The wafer comprises a third line in the first layer of the wafer. The third line has a terminal connected to the third line.