Patents by Inventor Effendi Leobandung

Effendi Leobandung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190198640
    Abstract: A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.
    Type: Application
    Filed: February 28, 2019
    Publication date: June 27, 2019
    Inventors: Pranita Kerber, Effendi Leobandung, Philip J. Oldiges
  • Publication number: 20190189783
    Abstract: A method is provided for use in forming a fin of a FinFET for an integrated circuit. The method comprises the steps of forming a hard mask on a substrate; forming an opening in the hard mask with a portion of the substrate exposed therein; forming a buffer on the exposed substrate within the opening in the hard mask; forming a mandrel at least in part on the buffer within the opening in the hard mask; forming a channel on a top and sides of the mandrel; removing the channel formed on the top of the mandrel without removing the channel formed on the sides of the mandrel; and removing the mandrel without removing the channel formed on the sides of the mandrel.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 20, 2019
    Inventor: Effendi Leobandung
  • Publication number: 20190189806
    Abstract: Devices and methods for forming a tight pitch stack nanowire without shallow trench isolation including a base nanosheet formed on a substrate. At least one fin are formed, and at least one dummy gate is formed over the at least two fins, on the base nanosheet, the at least two fins including at least two alternating layers of a first material and a second material. The base nanosheet is replaced with a blanket dielectric to form a shallow trench isolation (STI) around the at least one fin and around the at least one dummy gate. A gate replacement is performed to replace the at least one dummy gate and the second material with a gate conductor material and a gate cap to fouls gate structures.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 20, 2019
    Inventor: Effendi Leobandung
  • Publication number: 20190188556
    Abstract: A computer-implemented method, the method comprising: in an initial setup of weights for a floating gate including rows, columns, and a separate input line: comparing a current weight to a desired weight; performing a feedback to the input line to set a voltage to change the floating gate field effect transistor (FET) threshold voltage (VT) and the current weight; and checking that the current weight is within a predetermined tolerance of the desired weight; and performing a stochastic pulse update on the floating gate based on the checking.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Inventor: Effendi Leobandung
  • Patent number: 10326004
    Abstract: A method is provided for use in forming a fin of a FinFET for an integrated circuit. The method comprises the steps of forming a hard mask on a substrate; forming an opening in the hard mask with a portion of the substrate exposed therein; forming a buffer on the exposed substrate within the opening in the hard mask; forming a mandrel at least in part on the buffer within the opening in the hard mask; forming a channel on a top and sides of the mandrel; removing the channel formed on the top of the mandrel without removing the channel formed on the sides of the mandrel; and removing the mandrel without removing the channel formed on the sides of the mandrel.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10325852
    Abstract: A metallization scheme for vertical field effect transistors (FETs) is provided. By forming lower-level local interconnects connecting source regions located at bottom portions of semiconductor fins, and upper-level interconnects connecting adjacent metal gates located along sidewalls of channel regions of the semiconductor fins, electrical connections to the source regions and the metal gates can be provided through the lower-level local interconnects and the upper-level local interconnects, respectively. As a result, gate, source and drain contact structures are formed on the same side of vertical FETs.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Publication number: 20190180024
    Abstract: A method for determining the authenticity of a trackable item is provided. The method includes maintaining a database including first scan history data associated with a given integrated circuit associated with a given item. Second scan history data associated with the given integrated circuit is received. An authenticity of the given item is determined based on a comparison of the first scan history data to the second scan history data.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 13, 2019
    Inventor: Effendi Leobandung
  • Publication number: 20190182054
    Abstract: An approach is provided in which an information handling system performs multiple tests on a memory device using different supply voltage levels. The information handling system identifies a set of memory cells in the memory that produce a same set of results during each of the memory tests at the different supply voltage levels, and generates a random number based on a set of data values collected from the set of memory cells. In turn, the information handling system uses the random number generator in one or more processes executed by the information handling system.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventor: Effendi Leobandung
  • Publication number: 20190181245
    Abstract: Semiconductor devices and methods of forming the same include forming a second dielectric layer on sidewalls of a channel region of a semiconductor fin. The semiconductor fin is surrounded at a fin base by a first dielectric layer. The first dielectric layer is recessed to form a gap in the channel region of the semiconductor fin between the first dielectric layer and the second dielectric layer. Material from the semiconductor fin is etched away at the gap to separate the semiconductor fin from an underlying surface in the channel region. A gate stack is formed in the channel region that completely encircles the semiconductor fin.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Inventor: Effendi Leobandung
  • Publication number: 20190181043
    Abstract: A method for connecting metal layers in a mixed wire structure for a semiconductor substrate. A lower metal layer and a via in the mixed wired structure is formed in a dielectric structure on the semiconductor substrate, wherein a layer of a barrier metal is absent between the lower metal layer and the via. A trench is formed in the dielectric structure for an upper metal layer that contacts the via. A barrier metal layer is formed on the via and in the trench. The upper metal layer is formed after forming the barrier metal layer, wherein the barrier metal layer is located between the via and the upper metal layer.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Inventor: Effendi Leobandung
  • Patent number: 10319811
    Abstract: A finFET semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region further includes a condensed portion formed of a first semiconductor material and a second semiconductor material. The source/drain regions are formed of the first semiconductor material while excluding the second semiconductor material.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Effendi Leobandung, Gen Tsutsui, Tenko Yamashita
  • Patent number: 10315933
    Abstract: A structure for efficient water desalination, where as the evaporation chamber is at low pressure, and the condensation chamber is at high pressure. The evaporation chamber is connected to the condensation via a pump to pump the water vapor from evaporation chamber to condensation chamber.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 11, 2019
    Inventors: Effendi Leobandung, Nathan Samuel Leobandung
  • Patent number: 10319860
    Abstract: A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectric regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10319838
    Abstract: A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a sidewall of the structure defined by the silicon material; adjusting a growth condition to facilitate a first growth rate of the III-V material in directions along a surface of the sidewall and a second growth rate of the III-V material in a direction laterally from the surface of the sidewall, wherein the second growth rate is less than the first growth rate; and processing the silicon material and the III-V material to form a fin.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sanghoon Lee, Brent A. Wacaser, Devendra K. Sadana, Effendi Leobandung
  • Publication number: 20190170815
    Abstract: A probe card apparatus for wafer testing of a wafer under test, and a method of using the probe card for wafer testing. The probe card includes a printed circuit board having wafer testing circuitry. The probe card also includes a probe array including a slab having a plurality of probes, wherein each probe includes a volume of electrically-conductive fluid contained within a corresponding perforation of the slab that extends between a first surface and a second surface of the slab, wherein a first surface of each volume of electrically-conductive fluid substantially coincides with the first surface of the slab.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 6, 2019
    Inventor: Effendi Leobandung
  • Patent number: 10312160
    Abstract: A method of fabricating a transistor includes: forming an active device layer on a semiconductor substrate; patterning the active device layer to form fins; forming a first dielectric layer on an upper surface and sidewalls of the fins; forming a second dielectric layer on the first dielectric layer; forming openings through the first and second dielectric layers, exposing the underlying active device layer forming the fins; forming source/drain regions in the active device layer exposed through the respective openings; forming source/drain contacts on an upper surface of the source/drain regions; forming a second opening through the first and second dielectric layers, exposing the underlying active device layer adjacent to the source/drain regions; depositing a third dielectric layer in the second opening, on sidewalls and an upper surface of the fins; and forming a gate stack on the third dielectric layer.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10311225
    Abstract: A method for determining the authenticity of a trackable item is provided. The method includes maintaining a database including first scan history data associated with a given integrated circuit associated with a given item. Second scan history data associated with the given integrated circuit is received. An authenticity of the given item is determined based on a comparison of the first scan history data to the second scan history data.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Publication number: 20190164806
    Abstract: A method includes electrically joining two or more semiconductor chips to a silicon bridge chip, and electrically joining the two or more semiconductor chips to a substrate structure, the silicon bridge chip extends into a recess in the substrate structure such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure.
    Type: Application
    Filed: November 29, 2017
    Publication date: May 30, 2019
    Inventor: Effendi Leobandung
  • Publication number: 20190165144
    Abstract: A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventors: Tze-Chiang Chen, Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung
  • Publication number: 20190165118
    Abstract: Non-planar field effect transistor (FET) devices having wrap-around source/drain contacts are provided, as well as methods for fabricating non-planar FET devices with wrap-around source/drain contacts. A method includes forming a non-planar FET device on a substrate, which includes a semiconductor channel layer, and a gate structure in contact with upper and sidewall surfaces of the semiconductor channel layer. First and second source/drain regions are formed on opposite sides of the gate structure in contact with the semiconductor channel layer. First and second recesses are formed in an isolation layer below bottom surfaces of the first and second source/drain regions, respectively. A layer of metallic material is deposited to fill the first and second recesses in the isolation layer with metallic material and form first and second source/drain contacts which surround the first and second source/drain regions.
    Type: Application
    Filed: November 27, 2017
    Publication date: May 30, 2019
    Inventor: Effendi Leobandung