Abstract: Semiconductor devices include a semiconductor fin on a substrate. The semiconductor fin has channel region and source and drain regions. A gate stack is formed all around the channel region of the semiconductor fin, such that the channel region of the semiconductor fin is separated from the substrate. An interlayer dielectric is formed around the gate stack. At least a portion of the gate stack is formed in an undercut beneath the interlayer dielectric.

Abstract: A system comprises a processor, and a resistive processing resistive processing unit coupled to the processor. The resistive processing unit comprises an array of cells, wherein the cells respectively comprise resistive memory devices, wherein at least a portion of the resistive memory devices are programmable to store weight values of a given matrix in the array of cells. The processor is configured to store the given matrix in the array of cells of the resistive processing unit, and perform a calibration process to generate a first set of calibration parameters for calibrating forward pass matrix-vector multiplication operations performed on the stored matrix in the array of cells of the resistive processing unit, and a second set of calibration parameters for calibrating backward pass matrix-vector multiplication operations performed on a transpose of the stored matrix in the array of cells of the resistive processing unit.

Abstract: An analog circuit has a first plurality of transistors that are connected as a first selectable resistance in the analog circuit, and a second plurality of transistors that are connected as a second selectable resistance in the analog circuit. In an unlocked state of the analog circuit, the first selectable resistance matches the second selectable resistance within a designed ratio and tolerance. In a locked state of the analog circuit, the first selectable resistance and the second selectable resistance do not match within the designed ratio and tolerance. A controller retrieves a logic lock key from an off-chip memory and selects the first and second selectable resistances, thereby setting the analog circuit to its unlocked state, by sending respective first and second portions of the logic lock key to operate the first and second pluralities of transistors.

Abstract: Embodiments of the invention include a computer-implemented method that includes controlling, using a processor, a high-resolution optical inspection tool (HROIT) to identify a reference die tamper circuit on a reference die of a wafer; and controlling, using the processor, a low-resolution optical inspection tool (LROIT) to use the reference die tamper circuit to determine that the reference die tamper circuit is on a second die of the wafer.

Abstract: A semiconductor device is provided. The semiconductor device includes a first field effect device on a first region of a substrate, wherein a first gate structure and an electrostatic discharge device on a second region of the substrate, wherein a second gate structure for the electrostatic discharge device is separated from the substrate by the bottom dielectric layer, and a second source/drain for the electrostatic discharge device is in electrical contact with the substrate, wherein the second source/drain is doped with a second dopant type.

Abstract: A method for verifying semiconductor wafers includes receiving a semiconductor wafer including a plurality of layers. A first set of measurement data is obtained for at least one layer of the plurality of layers, where the first set of measurement data includes at least one previously recorded thickness measurement for one or more portions of the at least one layer. The first set of measurement data is compared to a second set of measurement data for the at least one layer. The second set of measurement data includes at least one new thickness measurement for the one or more portions of the at least one layer. The semiconductor wafer is determined to be an authentic wafer based on the second set of measurement data corresponding to the first set of measurement data, otherwise the semiconductor is determined to not be an authentic wafer.

Abstract: A timer circuit includes a plurality of n-type field effect transistors (NFETs) powered by a current source, a plurality of electromigration detection elements each electrically connected to a respective NFET of the plurality of NFETs, and a read-out circuit electrically connected to the plurality of electromigration detection elements to meter usage of each of the NFETs.

Abstract: A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised.

Abstract: An approach for validating a logic key in an IC (integrated circuit) is disclosed. One approach includes an IC comprising of key input circuit couple to a fuse check circuit; charge pump circuit coupled to the fuse check circuit and a switch matrix; and one or more antifuse circuit connected to the switch matrix. Another approach comprises of a method including, inputting a secret key by a user; determining status of one or more antifuse circuit; validating the secret key; in responsive to the secret key not matching an original secret key, determining whether antifuse threshold has been reached; in responsive to determining that the antifuse threshold has been reached, disabling the IC; in responsive to the secret key matching the original secret key, enabling the IC; and in responsive to determining that the antifuse threshold has not been reached, activating the antifuse circuit.

Abstract: A circuit for monitoring usage of an active field effect transistor (FET) includes the active FET and a reference FET, formed in a same structure as the active FET. The active FET and the reference FET both are pFET or both are nFET, and are stacked on each other at a common gate. The circuit also includes a differential current sense circuit (DCSC) and a plurality of switches for connecting terminals of the FETs to logic voltage, ground voltage, and/or the DCSC. The DCSC is configured to measure and compare currents through each of the active and reference FETs when a threshold voltage is applied to the common gate.

Abstract: A semiconductor device includes a plurality of storage elements formed on conductive structures and a cap layer located over the storage elements and the conductive structures. It further includes an interlevel dielectric (ILD) layer over the cap layer, where the ILD layer comprises trenches reaching a top portion of the storage elements, and via openings. The device also has a conductive material formed in the trenches and the via openings, where the conductive material makes contact with the storage elements and forms interlevel vias in the via openings.

Abstract: The embodiments herein describe authenticating a photomask used to fabricate an IC or a wafer. Because the IC may have been fabricated at a third-party IC manufacturer, the customer may want to ensure the manufacturer did not mistakenly use an incorrect mask, or that the mask was not altered or replaced with a rogue mask by a nefarious actor. That is, the embodiments herein can be used to identify when an IC manufacture (whether trusted or not) mistakenly used the wrong photomask, or to verify that a third-party IC manufacturer did not tamper with or replace the authentic photomask with a rogue mask. Advantageously, the embodiments herein can create a secure IC fabrication process to catch mistakes as well as ensure that non-trusted third-parties did not introduce defects into the IC.

Abstract: A semiconductor structure comprises a semiconductor substrate including a first silicon substrate component having a first crystalline orientation and a second silicon substrate component over the first silicon substrate and having a second crystalline orientation different from the first crystalline orientation. The semiconductor substrate defines a trench extending through the second silicon substrate component and at least partially within the first silicon substrate component. A gallium nitride structure is disposed within the trench of the semiconductor substrate.

Abstract: A redistribution layer for an integrated circuit package is provided. The redistribution layer includes a first conductive layer and a second layer disposed directly on the first conductive layer. The first conductive layer has a resistivity of less than 3.6*10?8 ?·m and has a thickness of greater than or equal to 1 ?m. The second layer includes tungsten. An integrated circuit package is also provided that includes the redistribution layer electrically connecting a first integrated circuit of the first integrated circuit package to a first input/output of a frame of the integrated circuit package. The frame is connected to the first integrated circuit. A method for manufacturing a redistribution layer is also provided.

Abstract: A stacked field effect transistor device is provided. The stacked field effect transistor device includes a lower semiconductor channel segment between a first pair of source/drains, and an upper semiconductor channel segment between a second pair of source/drains. The stacked device further includes a gate dielectric layer on the upper and lower semiconductor channel segments, and a first work function material layer on the gate dielectric layer on the lower semiconductor channel segment. The stacked device further includes a first conductive gate fill on the first work function material layer, and a replacement work function material layer on the gate dielectric layer on the upper semiconductor channel segment and the first conductive gate fill, wherein the replacement work function material layer is a different work function material from the first work function material layer. The device further includes a replacement conductive gate fill on the replacement work function material layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a metal-oxide-semiconductor field-effect-transistor (MOSFET) device electrically attachable to a first data line and a read-only memory (ROM) element. The ROM element is electrically interposable between the MOSFET device and a second data line. The ROM element includes first and second sets of memory cells in high and low resistance states, respectively, to form a secure identifier (ID).

Abstract: 3D NOR flash memory devices having vertically stacked memory cells are provided. In one aspect, a memory device includes: a word line/bit line stack with alternating word lines and bit lines separated by dielectric layers disposed on a substrate; a channel that extends vertically through the word line/bit line stack; and a floating gate stack surrounding the channel, wherein the floating gate stack is present between the word lines and the channel, and wherein the bit lines are in direct contact with both the channel and the floating gate stack. Techniques for configuring the memory device for neuromorphic computing are provided, as are methods of fabricating the memory device.

Abstract: A method for multiple copies of a set of multi-kernel set operations in a hardware accelerated neural network includes a word line for receiving a pixel value of an input image. A bit line communicates a modified pixel value. An analog memory cell including a first capacitor stores a first kernel weight of a first kernel in one of a plurality of kernel sets such that the pixel value is operated on by the first kernel weight to produce the modified pixel value. A charge connection connects the first capacitor to at least a second capacitor storing a second kernel weight of a related kernel of a second one of the plurality of kernel sets such that charge is shared between the first capacitor and at least the second capacitor to normalize the first kernel weight and the second kernel weight.

Abstract: Methods and systems of implementing a convolutional neural network are described. In an example, a structure may receive input signals and distribute the input signals to a plurality of unit cells. The structure may include a plurality of multi-kernel modules that may include a respective set of unit cells. A unit cell may correspond to an element of a kernel being implemented in the convolutional neural network and may include a storage component configured to store a weight of a corresponding element of the kernel. A first pass gate of the unit cell may be activated to pass a stored weight of the unit cell to a plurality of operation circuits in the corresponding unit cell, such that the stored weight may be applied to the input signals. The structure may generate a set of outputs based on the application of the stored weights to the input signals.

Abstract: A resistive processing unit cell includes a weight storage device to store a weight value of the resistive processing unit cell, and multiple circuit blocks. Each circuit block includes a weight update circuit coupled to dedicated update control lines, and a weight read circuit coupled to dedicated read control lines. The circuit blocks are configured to operate in parallel to (i) perform separate weight read operations in which each read circuit generates a read current based on a stored weight value, and outputs the read current on the dedicated read control lines of the read circuit, and (ii) perform separate weight update operations in which each update circuit receives respective update control signals on the dedicated update control lines, generates update currents based on the respective update control signals, and applies the update current to the weight storage device to adjust the weight value based on the update current.