Patents by Inventor Eiichi Nakano

Eiichi Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12199068
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: January 14, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Randon K. Richards, Aparna U. Limaye, Dong Soon Lim, Chan H. Yoo, Bret K. Street, Eiichi Nakano, Shijian Luo
  • Publication number: 20240387441
    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
  • Publication number: 20240355371
    Abstract: Methods, systems, and devices for data path signal amplification in coupled semiconductor systems are described. A semiconductor system may implement a first die including memory arrays and a second die including a host interface. The first die may include a first portion of a data path between the memory arrays and the host interface, including a first portion of data path signal amplification circuitry. The second die may include a second portion of the data path, including a second portion of data path signal amplification circuitry. The semiconductor system may implement fine-pitch interconnection between dies to support a relatively greater quantity of signal paths of the data path which, in some examples, may support reducing or eliminating serialization/deserialization circuitry associated with coarser interconnection. In some implementations, a semiconductor system may implement a switching component operable to switch between data paths having different amplification configurations of the dies.
    Type: Application
    Filed: March 15, 2024
    Publication date: October 24, 2024
    Inventors: James Brian Johnson, Brent Keeth, Kunal R. Parekh, Eiichi Nakano, Amy Rae Griffin
  • Publication number: 20240316311
    Abstract: A delivery device includes: an indwelling device including a stent body that is self-expandable; and a delivery catheter configured to separably support the indwelling device. The delivery catheter includes: a cover configured to cover at least a part of an axial range of the stent body; and an expansion restraining mechanism including a plurality of restraining wire rods configured to restrain expansion of the stent body by hooking a stent wire rod that constitutes the stent body. The plurality of restraining wire rods are configured to release restraint of the stent body by moving axially.
    Type: Application
    Filed: February 29, 2024
    Publication date: September 26, 2024
    Inventors: Yuki TOYODA, Eiichi NAKANO
  • Publication number: 20240313098
    Abstract: Methods, systems, and devices for transistor architectures in coupled semiconductor systems are described. A memory system may be formed from multiple semiconductor components (e.g., multiple dies, multiple wafers) that are coupled together, with different semiconductor components implementing different techniques for transistor formation. For example, a first die may include a memory array and first circuitry configured to access the memory array, and a second die coupled with the first die may include second circuitry configured to access the memory array. The first circuitry may include transistors formed in accordance with a first fabrication technique (e.g., to form a first type of transistors) and the second circuitry may include transistors formed in accordance with a second fabrication technique (e.g., to form a second type of transistors). The dies may be coupled in a manner that provides an electrical coupling between the first circuitry and the second circuitry.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 19, 2024
    Inventors: James Brian Johnson, Brent Keeth, Kunal R. Parekh, Eiichi Nakano, Amy Rae Griffin
  • Patent number: 12051670
    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
  • Publication number: 20240237363
    Abstract: Methods, systems, and devices for modular die configurations for multi-channel memory are described. A semiconductor component (e.g., a semiconductor wafer) may be configured with multiple rows and multiple columns of memory arrays, and associated channels. A row of memory arrays may be associated with a contact region extending along the row direction. The semiconductor component may also include control regions extending along the column direction between at least some of the columns of memory arrays. Each control region may include control circuitry for operating memory arrays on one or both sides of the control region. The channels and memory arrays of the semiconductor wafer may be grouped into one or more independently-operable memory dies, with each memory die having at least a portion of a control region and at least a portion of a contact region for operating the memory arrays of the memory die.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 11, 2024
    Inventors: James Brian Johnson, Brent Keeth, Ameen D. Akel, Kunal R. Parekh, Amy Rae Griffin, Eiichi Nakano
  • Publication number: 20240203827
    Abstract: Semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. The semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. The microchannel can be configured beneath the memory device and/or the logic device.
    Type: Application
    Filed: January 18, 2024
    Publication date: June 20, 2024
    Inventors: Xiaopeng Qu, Hyunsuk Chun, Eiichi Nakano
  • Publication number: 20240194287
    Abstract: Methods, systems, and devices for repair techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of circuitry configured to access the set of memory arrays, and a second die may include a second portion of circuitry configured to access the set of memory arrays. The second portion of the circuitry (e.g., of the second die) may be configured to support various repair techniques for operations with the set of memory arrays, including techniques in response to column failures or serialization failures associated with the first die, or in response to contact or other interconnection failures with or between the first die and the second die, among other techniques that may be differentiated based on an attribution of error conditions.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 13, 2024
    Inventors: James Brian Johnson, Brent Keeth, Kunal R. Parekh, Eiichi Nakano, Amy Rae Griffin
  • Publication number: 20240186274
    Abstract: Methods, systems, and devices for thermal distribution techniques in coupled semiconductor systems are described. A semiconductor system may be formed by coupling various semiconductor components with one another, and may also implement a semiconductor material to support a thermal path having a thermal conductivity that is relatively close to a thermal conductivity through the coupled semiconductor components of the semiconductor system. Such a semiconductor material may be located in regions of the semiconductor system that are otherwise unoccupied by functional (e.g., electrically operable) semiconductor components and may, in some examples, be electrically inoperable (e.g., may lack functional circuitry). For implementations in which functional semiconductor components are directly coupled (e.g., by fusion bonding or hybrid bonding techniques), the semiconductor material may also be directly coupled with at least one of the semiconductor components.
    Type: Application
    Filed: November 29, 2023
    Publication date: June 6, 2024
    Inventors: Amy Rae Griffin, Brent Keeth, Kunal R. Parekh, Eiichi Nakano, James Brian Johnson, Ameen D. Akel
  • Publication number: 20240176523
    Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of the circuitry configured to access the set of memory arrays, and a second die may include a second portion of the circuitry configured to access the set of memory arrays. The first portion and the second portion of the circuitry configured to access a set of memory arrays may be communicatively coupled between the dies using various interconnection techniques, such as a fusion of conductive contacts of the respective memory dies. In some examples, the second die may also include the host itself (e.g., a host processor).
    Type: Application
    Filed: November 21, 2023
    Publication date: May 30, 2024
    Inventors: James Brian Johnson, Brent Keeth, Kunal R. Parekh, Eiichi Nakano, Amy Rae Griffin, Ameen D. Akel
  • Publication number: 20240170435
    Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.
    Type: Application
    Filed: January 22, 2024
    Publication date: May 23, 2024
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Publication number: 20240071556
    Abstract: Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: James Brian Johnson, Kunal R. Parekh, Brent Keeth, Eiichi Nakano, Amy Rae Griffin
  • Patent number: 11915997
    Abstract: Semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. The semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. The microchannel can be configured beneath the memory device and/or the logic device.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Xiaopeng Qu, Hyunsuk Chun, Eiichi Nakano
  • Publication number: 20240063172
    Abstract: A stacked semiconductor device and systems and methods for producing the same are disclosed here. In some embodiments, the method includes aligning a first array of bond pads on an upper surface of a first semiconductor substrate with a second array of bond pads on a lower surface of a second semiconductor substrate. The method then includes annealing the stacked semiconductor device to bond the upper surface of the first semiconductor substrate to the lower surface of the second semiconductor substrate. The annealing results in at least one void between the upper surface and the lower surface that includes a layer of diffused metal. The layer of diffused metal extends from a first individual bond pad towards a second individual bond pad and forms an electrical or thermal short. The method then includes exposing the stacked semiconductor device to microwave radiation to excite a chemical constituent present in the void.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 22, 2024
    Inventors: Chia Jung Hsu, Eiichi Nakano
  • Patent number: 11881468
    Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: January 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Publication number: 20230411299
    Abstract: Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 ?m). Adjacent passivation material may also be thin (e.g., less than about 0.2 ?m). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Inventor: Eiichi Nakano
  • Publication number: 20230395545
    Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Bharat Bhushan, Akshay N. Singh, Bret K. Street, Debjit Datta, Eiichi Nakano
  • Publication number: 20230372130
    Abstract: An object is to provide a stent having, in a well-balanced manner, a high expansion force that enables the stent to come into close contact with an inner wall of a tubular organ, such as a digestive tract, to sufficiently expand a constricted part and good flexibility by which none of an ulcer and a perforation is generated at sites with which both end parts of the stent come into contact even when the stent is placed in a bent tubular organ. A stent of the disclosure is a stent formed in a tubular shape by braiding one or more wire rods. A radial force (RF) ranges from 0.02 N/mm to 0.04 N/mm, and a ratio (RF/AF) of the radial force (RF) to an axial force (AF) is 0.14 mm?1 or more. The stent of the disclosure preferably has a shortening of 35% or less.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Inventors: Eiichi NAKANO, Masamune SAKAI, Fumiaki KOBAYASHI
  • Patent number: 11817420
    Abstract: A stacked semiconductor device and systems and methods for producing the same are disclosed here. In some embodiments, the method includes aligning a first array of bond pads on an upper surface of a first semiconductor substrate with a second array of bond pads on a lower surface of a second semiconductor substrate. The method then includes annealing the stacked semiconductor device to bond the upper surface of the first semiconductor substrate to the lower surface of the second semiconductor substrate. The annealing results in at least one void between the upper surface and the lower surface that includes a layer of diffused metal. The layer of diffused metal extends from a first individual bond pad towards a second individual bond pad and forms an electrical or thermal short. The method then includes exposing the stacked semiconductor device to microwave radiation to excite a chemical constituent present in the void.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: November 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Chia Jung Hsu, Eiichi Nakano