Patents by Inventor Eiichi Nakano

Eiichi Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220028820
    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 27, 2022
    Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
  • Publication number: 20210407889
    Abstract: Semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. The semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. The microchannel can be configured beneath the memory device and/or the logic device.
    Type: Application
    Filed: August 11, 2020
    Publication date: December 30, 2021
    Inventors: Xiaopeng Qu, Hyunsuk Chun, Eiichi Nakano
  • Patent number: 11189588
    Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Patent number: 11171118
    Abstract: Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy along a lateral plane and across the substrate. The thermal energy is transferred along a non-lateral direction from the semiconductor device to the graphene layer using one or more thermal connectors.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Owen R. Fay, Eiichi Nakano
  • Patent number: 11139262
    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
  • Publication number: 20210272872
    Abstract: Semiconductor devices including materials for thermal management, and associated systems and methods, are described herein. In some embodiments, a semiconductor package includes a first semiconductor die coupled to a second semiconductor die by a plurality of interconnect structures. A thermal material can be positioned between the first and second semiconductor dies. The thermal material can include an array of heat transfer elements embedded in a supporting matrix material. The array of heat transfer elements can include at least one vacant region aligned with at least one of the interconnect structures.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Inventors: Xiaopeng Qu, Hyunsuk Chun, Eiichi Nakano, Amy R. Griffin
  • Publication number: 20210240344
    Abstract: Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm2).
    Type: Application
    Filed: January 29, 2021
    Publication date: August 5, 2021
    Inventors: Brent Keeth, Bambi L. DeLaRosa, Eiichi Nakano
  • Patent number: 11069612
    Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Publication number: 20210118852
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.
    Type: Application
    Filed: July 27, 2020
    Publication date: April 22, 2021
    Inventors: Owen R. Fay, Randon K. Richards, Aparna U. Limaye, Dong Soon Lim, Chan H. Yoo, Bret K. Street, Eiichi Nakano, Shijian Luo
  • Patent number: 10943860
    Abstract: A semiconductor device assembly that includes a flexible member having a first portion connected to a substrate and a connector attached to a second portion of the flexible member. The connector is electrically connected to the substrate via a conducting layer within the flexible member. The substrate may be a semiconductor device, such as a chip. The connector may be configured to connect the semiconductor device to another semiconductor device assembly or a system board, such as a printed circuit board. A material may encapsulate at least a portion of the substrate of the semiconductor assembly. The semiconductor device assembly may be formed by selectively connecting the flexible member to a first substrate. A second substrate and connector may then be connected to the flexible member. A release layer may be used to release the assembly of the second substrate, flexible member, and connector from the first substrate.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: March 9, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Chan H. Yoo, Eiichi Nakano
  • Publication number: 20210057342
    Abstract: Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 ?m). Adjacent passivation material may also be thin (e.g., less than about 0.2 ?m). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 25, 2021
    Inventor: Eiichi Nakano
  • Publication number: 20210005575
    Abstract: Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy along a lateral plane and across the substrate. The thermal energy is transferred along a non-lateral direction from the semiconductor device to the graphene layer using one or more thermal connectors.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 7, 2021
    Inventors: Chan H. Yoo, Owen R. Fay, Eiichi Nakano
  • Patent number: 10854549
    Abstract: Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 ?m). Adjacent passivation material may also be thin (e.g., less than about 0.2 ?m). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Patent number: 10797018
    Abstract: Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Publication number: 20200266173
    Abstract: Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Inventor: Eiichi Nakano
  • Publication number: 20200258859
    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 13, 2020
    Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
  • Publication number: 20200211967
    Abstract: Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 ?m). Adjacent passivation material may also be thin (e.g., less than about 0.2 ?m). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventor: Eiichi Nakano
  • Publication number: 20200211996
    Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Patent number: 10651050
    Abstract: Semiconductor device packages may include a support structure having electrical connections therein. Semiconductor device modules may be located on a surface of the support structure. A molding material may at least partially surround each semiconductor module on the surface of the support structure. A thermal management device may be operatively connected to the semiconductor device modules on a side of the semiconductor device modules opposite the support structure. At least some of the semiconductor device modules may include a stack of semiconductor dice, at least two semiconductor dice in the stack being secured to one another by diffusion of electrically conductive material of electrically conductive elements into one another.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Publication number: 20200126907
    Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 23, 2020
    Inventors: Eiichi Nakano, Mark E. Tuttle