Patents by Inventor Eiji Mochizuki

Eiji Mochizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220222777
    Abstract: An image processing device combines a plurality of time-series images to generate a composite image with a higher resolution than a resolution of the plurality of images. The image processing device includes a processor that includes hardware and that is configured to: detect depth information of at least one image of the plurality of images; and set the number of images to be combined for generating the composite image on the basis of the detected depth information. The depth information indicates a depth of a captured scene of the at least one image. The processor is configured to reduce the number of images as the depth of the captured scene increases.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 14, 2022
    Applicant: OLYMPUS CORPORATION
    Inventors: Kosuke KAJIMURA, Ryosuke MOCHIZUKI, Kenichi ONOMURA, Eiji FURUKAWA
  • Publication number: 20210364581
    Abstract: An improved system for measuring current within a power semiconductor module is disclosed, where the system is integrated within the power module. The system includes a point field detector sensing a magnetic field resulting from current flowing in one phase of the module. A lead frame conductor may be provided to shape the magnetic field and minimize the influence of cross-coupled magnetic fields from currents conducted in other power semiconductor devices within one phase of the module. Optionally, a second point field detector may be provided at a second location within the module to sense a magnetic field resulting from the current flowing in the same phase of the module. Each phase of the power module includes at least one point field detector. A decoupling circuit is provided to decouple multiple currents flowing within the same phase or to decouple currents flowing within different phases of the power module.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Robert D. Lorenz, Minhao Sheng, Hiroyuki Nogawa, Yoshinari Ikeda, Eiji Mochizuki
  • Patent number: 11085977
    Abstract: An improved system for measuring current within a power semiconductor module is disclosed, where the system is integrated within the power module. The system includes a point field detector sensing a magnetic field resulting from current flowing in one phase of the module. A lead frame conductor may be provided to shape the magnetic field and minimize the influence of cross-coupled magnetic fields from currents conducted in other power semiconductor devices within one phase of the module. Optionally, a second point field detector may be provided at a second location within the module to sense a magnetic field resulting from the current flowing in the same phase of the module. Each phase of the power module includes at least one point field detector. A decoupling circuit is provided to decouple multiple currents flowing within the same phase or to decouple currents flowing within different phases of the power module.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 10, 2021
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Robert D. Lorenz, Minhao Sheng, Hiroyuki Nogawa, Yoshinari Ikeda, Eiji Mochizuki
  • Publication number: 20210242103
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.
    Type: Application
    Filed: January 5, 2021
    Publication date: August 5, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yoshinari IKEDA, Tatsuo NISHIZAWA, Motohito HORI, Eiji MOCHIZUKI
  • Publication number: 20210242156
    Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.
    Type: Application
    Filed: December 31, 2020
    Publication date: August 5, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi KATO, Yoshinari IKEDA, Tatsuo NISHIZAWA, Eiji MOCHIZUKI
  • Patent number: 10355089
    Abstract: A MOS gate structure including a p base region, a p epitaxial layer, an n++ source region, a p+ contact region, an n inversion region, a gate insulating film, and a gate electrode and a front surface electrode are provided on the front surface of an epitaxial substrate obtained by depositing an n? epitaxial layer on the front surface of a SiC substrate. A first metal film is provided on the front surface electrode so as to cover 10% or more, preferably, 60% to 90%, of an entire upper surface of the front surface electrode. The SiC-MOSFET is manufactured by forming a rear surface electrode, forming the first metal film on the surface of the front surface electrode, and annealing in a N2 atmosphere. According to this structure, it is possible to suppress a reduction in gate threshold voltage in a semiconductor device using a SiC semiconductor.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Saito, Masaaki Ogino, Eiji Mochizuki, Yoshikazu Takahashi
  • Patent number: 10297527
    Abstract: A semiconductor device includes a radiation plate having a rear surface roughened by a plurality of dents that overlap with each other; a laminated substrate provided on a front surface of the radiation plate and including an insulating plate, a circuit board provided on a front surface of the insulating plate, and a metal plate provided on a rear surface of the insulating plate; a semiconductor chip provided on the circuit board; a radiator; and a heat radiating material retained between the rear surface of the radiation plats and the radiator. The plurality of dents that roughen the rear surface of the radiation plate provides the rear surface with an arithmetic average roughness ranging from 1 ?m to 10 ?m, and each of the dents has a maximum dent depth ranging from 12 ?m to 71.5 ?m, and a dent width ranging from 0.17 mm to 0.72 mm.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Saito, Fumihiko Momose, Yoshitaka Nishimura, Eiji Mochizuki
  • Publication number: 20180329002
    Abstract: An improved system for measuring current within a power semiconductor module is disclosed, where the system is integrated within the power module. The system includes a point field detector sensing a magnetic field resulting from current flowing in one phase of the module. A lead frame conductor may be provided to shape the magnetic field and minimize the influence of cross-coupled magnetic fields from currents conducted in other power semiconductor devices within one phase of the module. Optionally, a second point field detector may be provided at a second location within the module to sense a magnetic field resulting from the current flowing in the same phase of the module. Each phase of the power module includes at least one point field detector. A decoupling circuit is provided to decouple multiple currents flowing within the same phase or to decouple currents flowing within different phases of the power module.
    Type: Application
    Filed: May 15, 2017
    Publication date: November 15, 2018
    Inventors: Robert D. Lorenz, Minhao Sheng, Hiroyuki Nogawa, Yoshinari Ikeda, Eiji Mochizuki
  • Patent number: 10128166
    Abstract: A power semiconductor module includes a cooler; a plurality of power semiconductor units fixed on the cooler; and a bus bar unit connected electrically to the plurality of power semiconductor units. Each of the plurality of power semiconductor units includes a multilayered substrate including a circuit plate, an insulating plate, and a metal plate laminated in respective order; a semiconductor element fixed to the circuit plate; a wiring member having a printed circuit board and a plurality of conductive posts; external terminals connected electrically and mechanically to the circuit plate; and an insulating sealing material. The bus bar unit includes a plurality of bus bars mutually connecting the external terminals of the plurality of power semiconductor units.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshikazu Takahashi, Eiji Mochizuki, Yoshitaka Nishimura, Yoshinari Ikeda
  • Patent number: 10090222
    Abstract: A semiconductor device includes: a semiconductor module and a heat dissipation sheet attached to a bottom surface of the semiconductor module, the heat dissipation sheet including: a sheet-shaped first conduction part that has a first main surface bonded to the bottom surface of the circuit substrate, a thermal conductivity of the first conduction part in directions along the first main surface being higher than a thermal conductivity of the first conduction part in a thickness direction; and a sheet-shaped second conduction part that is provided next to the first conduction part at an end of the first conduction part and that has a second main surface continuing from the first main surface, a thermal conductivity of the second conduction part in a thickness direction being higher than a thermal conductivity of the second conduction part in directions along the second main surface.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 2, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akira Hirao, Eiji Mochizuki, Fumihiko Momose
  • Patent number: 10090223
    Abstract: A semiconductor device includes a heat-dissipating base, a first conductive layer bonded to the top surface of the heat-dissipating base, an AlN insulating substrate bonded to the top surface of the first conductive layer, and an electrode terminal having one edge bending to form a bonding edge whose bottom surface faces the top surface of the second conductive layer and is solid-state bonded to a portion of the top surface of the second conductive layer. The crystal grain diameter at the bonded interface of the second conductive layer and electrode terminal is less than or equal to 1 ?m, and indentations from the ultrasonic horn are left in the top surface of the bonding edge.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 2, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Fumihiko Momose, Hiroyuki Nogawa, Yoshitaka Nishimura, Eiji Mochizuki
  • Publication number: 20180240730
    Abstract: A semiconductor device includes: a semiconductor module and a heat dissipation sheet attached to a bottom surface of the semiconductor module, the heat dissipation sheet including: a sheet-shaped first conduction part that has a first main surface bonded to the bottom surface of the circuit substrate, a thermal conductivity of the first conduction part in directions along the first main surface being higher than a thermal conductivity of the first conduction part in a thickness direction; and a sheet-shaped second conduction part that is provided next to the first conduction part at an end of the first conduction part and that has a second main surface continuing from the first main surface, a thermal conductivity of the second conduction part in a thickness direction being higher than a thermal conductivity of the second conduction part in directions along the second main surface.
    Type: Application
    Filed: January 5, 2018
    Publication date: August 23, 2018
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Akira HIRAO, Eiji MOCHIZUKI, Fumihiko MOMOSE
  • Patent number: 9999146
    Abstract: A semiconductor module includes sealing resin from which a main terminal protrudes, which seals an insulating substrate. The module includes a semiconductor element and a wiring substrate. The sealing resin has a nut housing portion in which a nut is disposed. The semiconductor module also has a busbar terminal to which a main terminal that protrudes from the sealing resin is electrically connected and which has an insertion hole facing the nut.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: June 12, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshinari Ikeda, Hideyo Nakamura, Eiji Mochizuki, Tatsuo Nishizawa
  • Patent number: 9824950
    Abstract: A semiconductor device according to the invention includes an insulating substrate including an insulating plate, a circuit pattern that is formed on a front surface of the insulating plate, and a radiator plate that is fixed to a rear surface of the insulating plate, a semiconductor chip that is fixed to the circuit pattern, an external lead terminal that is connected to a surface electrode of the semiconductor chip through a wiring line, a molding resin that covers the insulating substrate, the semiconductor chip, the wiring line, and the external lead terminal such that a rear surface of the radiator plate and a portion of the external lead terminal are exposed, and an anchor layer including a stripe-shaped concave portion which is formed in the circuit pattern by laser beam irradiation.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: November 21, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kyohei Fukuda, Tatsuo Nishizawa, Yuhei Nishida, Eiji Mochizuki
  • Publication number: 20170317008
    Abstract: A semiconductor device includes a heat-dissipating base, a first conductive layer bonded to the top surface of the heat-dissipating base, an AlN insulating substrate bonded to the top surface of the first conductive layer, and an electrode terminal having one edge bending to form a bonding edge whose bottom surface faces the top surface of the second conductive layer and is solid-state bonded to a portion of the top surface of the second conductive layer. The crystal grain diameter at the bonded interface of the second conductive layer and electrode terminal is less than or equal to 1 ?m, and indentations from the ultrasonic horn are left in the top surface of the bonding edge.
    Type: Application
    Filed: March 8, 2017
    Publication date: November 2, 2017
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Fumihiko MOMOSE, Hiroyuki NOGAWA, Yoshitaka NISHIMURA, Eiji MOCHIZUKI
  • Patent number: 9786587
    Abstract: A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L2 of each of the implant pins into corresponding cylindrical terminals is adjustable, so that total length of the implant pin and cylindrical terminal which are press-fitted to each other matches up with the distance between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and an implant board.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: October 10, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tatsuo Nishizawa, Shinji Tada, Yoshito Kinoshita, Yoshinari Ikeda, Eiji Mochizuki
  • Publication number: 20170181300
    Abstract: A semiconductor module includes sealing resin from which a main terminal protrudes, which seals an insulating substrate. The module includes a semiconductor element and a wiring substrate. The sealing resin has a nut housing portion in which a nut is disposed. The semiconductor module also has a busbar terminal to which a main terminal that protrudes from the sealing resin is electrically connected and which has an insertion hole facing the nut.
    Type: Application
    Filed: October 27, 2016
    Publication date: June 22, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito HORI, Yoshinari IKEDA, Hideyo NAKAMURA, Eiji MOCHIZUKI, Tatsuo NISHIZAWA
  • Publication number: 20170077009
    Abstract: A semiconductor device includes a radiation base having a plurality of dents formed and overlapped with each other in the rear surface thereof. The dents in the rear surface of the radiation base are formed by performing a shot peening process on the rear surface of the radiation base. The average particle size of the shot material is preferably set to 0.3 to 6 mm when a shot material is SUS, the processing time is 20 seconds, and the ultrasonic wave amplitude is 70 ?m as the processing conditions of the shot peening process. If a radiation fin is provided via a thermal compound in the rear surface of the radiation base which has been subjected to the shot peening process under such processing conditions, the adhesion to the thermal compound will improve due to an anchor effect of the overlapped dents of the radiation base.
    Type: Application
    Filed: August 1, 2016
    Publication date: March 16, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi SAITO, Fumihiko MOMOSE, Yoshitaka NISHIMURA, Eiji MOCHIZUKI
  • Patent number: 9579746
    Abstract: A thermocompression bonding structure includes a first member and a second member having a linear expansion coefficient different from that of the first member; and metal fine particles interposed between the first and second members as a bonding material to thermocompression bond the two members. The two members are disposed to apply thermal stress generating between the first member and the second member as pressurizing force on a bonding surface between the two members, and to increase temperature to thermocompression bond the first member and the second member.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: February 28, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshito Kinoshita, Eiji Mochizuki, Tatsuo Nishizawa, Shinji Tada
  • Publication number: 20160343641
    Abstract: A power semiconductor module includes a cooler; a plurality of power semiconductor units fixed on the cooler; and a bus bar unit connected electrically to the plurality of power semiconductor units. Each of the plurality of power semiconductor units includes a multilayered substrate including a circuit plate, an insulating plate, and a metal plate laminated in respective order; a semiconductor element fixed to the circuit plate; a wiring member having a printed circuit board and a plurality of conductive posts; external terminals connected electrically and mechanically to the circuit plate; and an insulating sealing material. The bus bar unit includes a plurality of bus bars mutually connecting the external terminals of the plurality of power semiconductor units.
    Type: Application
    Filed: August 8, 2016
    Publication date: November 24, 2016
    Inventors: Motohito HORI, Yoshikazu TAKAHASHI, Eiji MOCHIZUKI, Yoshitaka NISHIMURA, Yoshinari IKEDA