Patents by Inventor Eiji Mochizuki
Eiji Mochizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170077009Abstract: A semiconductor device includes a radiation base having a plurality of dents formed and overlapped with each other in the rear surface thereof. The dents in the rear surface of the radiation base are formed by performing a shot peening process on the rear surface of the radiation base. The average particle size of the shot material is preferably set to 0.3 to 6 mm when a shot material is SUS, the processing time is 20 seconds, and the ultrasonic wave amplitude is 70 ?m as the processing conditions of the shot peening process. If a radiation fin is provided via a thermal compound in the rear surface of the radiation base which has been subjected to the shot peening process under such processing conditions, the adhesion to the thermal compound will improve due to an anchor effect of the overlapped dents of the radiation base.Type: ApplicationFiled: August 1, 2016Publication date: March 16, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takashi SAITO, Fumihiko MOMOSE, Yoshitaka NISHIMURA, Eiji MOCHIZUKI
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Patent number: 9579746Abstract: A thermocompression bonding structure includes a first member and a second member having a linear expansion coefficient different from that of the first member; and metal fine particles interposed between the first and second members as a bonding material to thermocompression bond the two members. The two members are disposed to apply thermal stress generating between the first member and the second member as pressurizing force on a bonding surface between the two members, and to increase temperature to thermocompression bond the first member and the second member.Type: GrantFiled: March 25, 2014Date of Patent: February 28, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yoshito Kinoshita, Eiji Mochizuki, Tatsuo Nishizawa, Shinji Tada
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Publication number: 20160343641Abstract: A power semiconductor module includes a cooler; a plurality of power semiconductor units fixed on the cooler; and a bus bar unit connected electrically to the plurality of power semiconductor units. Each of the plurality of power semiconductor units includes a multilayered substrate including a circuit plate, an insulating plate, and a metal plate laminated in respective order; a semiconductor element fixed to the circuit plate; a wiring member having a printed circuit board and a plurality of conductive posts; external terminals connected electrically and mechanically to the circuit plate; and an insulating sealing material. The bus bar unit includes a plurality of bus bars mutually connecting the external terminals of the plurality of power semiconductor units.Type: ApplicationFiled: August 8, 2016Publication date: November 24, 2016Inventors: Motohito HORI, Yoshikazu TAKAHASHI, Eiji MOCHIZUKI, Yoshitaka NISHIMURA, Yoshinari IKEDA
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Patent number: 9504154Abstract: A semiconductor device composed of a plurality of semiconductor modules exhibiting a large current carrying capacity for a semiconductor device as a whole is disclosed. The connection between the plurality of semiconductor modules is conducted by means of optimum construction suited to the semiconductor device. The device comprises a semiconductor module having externally connecting terminals protruding out of a casing, bus bars electrically connecting the specific externally connecting terminals of the plurality of semiconductor modules arranged in parallel with each other, and a semiconductor module case covering and fastening the plurality of semiconductor modules connected with the bus bars. The bus bars and the externally connecting terminals of the semiconductor modules are joined by means of laser welding.Type: GrantFiled: May 28, 2014Date of Patent: November 22, 2016Assignee: Fuji Electric Co., Ltd.Inventors: Shinji Tada, Eiji Mochizuki, Hideyo Nakamura, Masafumi Horio
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Publication number: 20160322287Abstract: A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L2 of each of the implant pins into corresponding cylindrical terminals is adjustable, so that total length of the implant pin and cylindrical terminal which are press-fitted to each other matches up with the distance between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and an implant board.Type: ApplicationFiled: July 8, 2016Publication date: November 3, 2016Inventors: Tatsuo NISHIZAWA, Shinji TADA, Yoshito KINOSHITA, Yoshinari IKEDA, Eiji MOCHIZUKI
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Patent number: 9431326Abstract: In a semiconductor device, semiconductor chips and lead frames are soldered at the same time on an insulating circuit board by one reflow soldering, and the positions of the externally led out lead frames undergo no change. In manufacturing the semiconductor device, after power semiconductor chips and control ICs are mounted on an insulating circuit board, and lead frames are disposed thereon, the semiconductor chips and lead frames are soldered at the same time on the insulating circuit board by one reflow soldering. Furthermore, after a primary bending work is carried out on the lead frames, and a terminal case is mounted over the insulating circuit board, a secondary bending work is carried out on the lead frames.Type: GrantFiled: March 30, 2012Date of Patent: August 30, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Toshio Denta, Tadanori Yamada, Eiji Mochizuki
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Patent number: 9406603Abstract: A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L2 of each of the implant pins into corresponding cylindrical terminals is adjustable, so that total length of the implant pin and cylindrical terminal which are press-fitted to each other matches up with the distance between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and an implant board.Type: GrantFiled: May 12, 2014Date of Patent: August 2, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tatsuo Nishizawa, Shinji Tada, Yoshito Kinoshita, Yoshinari Ikeda, Eiji Mochizuki
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Patent number: 9269644Abstract: A method for producing a semiconductor device includes solder-connecting a semiconductor chip, onto an insulating substrate including a ceramic board and having conductor layers on two surfaces thereof, with a lead-free solder; warping a radiating base such that a surface of the radiating base on a side opposite to the insulating substrate is convex; and solder-connecting the insulating substrate onto the warped radiating base with the lead-free solder so as to provide a substantially flat solder-connected radiating base.Type: GrantFiled: September 3, 2013Date of Patent: February 23, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yoshitaka Nishimura, Akira Morozumi, Kazunaga Ohnishi, Eiji Mochizuki, Yoshikazu Takahashi
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Publication number: 20150372095Abstract: A MOS gate structure including a p base region, a p epitaxial layer, an n++ source region, a p+ contact region, an n inversion region, a gate insulating film, and a gate electrode and a front surface electrode are provided on the front surface of an epitaxial substrate obtained by depositing an n? epitaxial layer on the front surface of a SiC substrate. A first metal film is provided on the front surface electrode so as to cover 10% or more, preferably, 60% to 90%, of an entire upper surface of the front surface electrode. The SiC-MOSFET is manufactured by forming a rear surface electrode, forming the first metal film on the surface of the front surface electrode, and annealing in a N2 atmosphere. According to this structure, it is possible to suppress a reduction in gate threshold voltage in a semiconductor device using a SiC semiconductor.Type: ApplicationFiled: August 31, 2015Publication date: December 24, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takashi SAITO, Masaaki OGINO, Eiji MOCHIZUKI, Yoshikazu TAKAHASHI
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Publication number: 20150187671Abstract: A semiconductor device according to the invention includes an insulating substrate including an insulating plate, a circuit pattern that is formed on a front surface of the insulating plate, and a radiator plate that is fixed to a rear surface of the insulating plate, a semiconductor chip that is fixed to the circuit pattern, an external lead terminal that is connected to a surface electrode of the semiconductor chip through a wiring line, a molding resin that covers the insulating substrate, the semiconductor chip, the wiring line, and the external lead terminal such that a rear surface of the radiator plate and a portion of the external lead terminal are exposed, and an anchor layer including a stripe-shaped concave portion which is formed in the circuit pattern by laser beam irradiation.Type: ApplicationFiled: March 12, 2015Publication date: July 2, 2015Inventors: Kyohei FUKUDA, Tatsuo NISHIZAWA, Yuhei NISHIDA, Eiji MOCHIZUKI
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Patent number: 8944310Abstract: A soldering method achieves little void and good joint condition in soldering an insulated circuit board and a semiconductor chip using a tin-high antimony solder material. A method of manufacturing a semiconductor device includes the steps of preparing a solder plate having a U-shape; mounting the solder plate on a substrate; mounting a semiconductor chip on the solder plate; fusing the solder plate in a reducing gas atmosphere; and reducing a pressure of the reducing gas atmosphere to a pressure lower than the atmospheric pressure when melting the solder plate.Type: GrantFiled: February 7, 2014Date of Patent: February 3, 2015Assignee: Fuji Electric Co., Ltd.Inventors: Takeshi Matsushita, Eiji Mochizuki, Tatsuo Nishizawa, Shunsuke Saito
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Publication number: 20140355219Abstract: A semiconductor device composed of a plurality of semiconductor modules exhibiting a large current carrying capacity for a semiconductor device as a whole is disclosed. The connection between the plurality of semiconductor modules is conducted by means of optimum construction suited to the semiconductor device. The device comprises a semiconductor module having externally connecting terminals protruding out of a casing, bus bars electrically connecting the specific externally connecting terminals of the plurality of semiconductor modules arranged in parallel with each other, and a semiconductor module case covering and fastening the plurality of semiconductor modules connected with the bus bars. The bus bars and the externally connecting terminals of the semiconductor modules are joined by means of laser welding.Type: ApplicationFiled: May 28, 2014Publication date: December 4, 2014Applicant: Fuji Electric Co., Ltd.Inventors: Shinji TADA, Eiji MOCHIZUKI, Hideyo NAKAMURA, Masafumi HORIO
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Publication number: 20140301769Abstract: A thermocompression bonding structure includes a first member and a second member having a linear expansion coefficient different from that of the first member; and metal fine particles interposed between the first and second members as a bonding material to thermocompression bond the two members. The two members are disposed to apply thermal stress generating between the first member and the second member as pressurizing force on a bonding surface between the two members, and to increase temperature to thermocompression bond the first member and the second member.Type: ApplicationFiled: March 25, 2014Publication date: October 9, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoshito KINOSHITA, Eiji MOCHIZUKI, Tatsuo NISHIZAWA, Shinji TADA
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Publication number: 20140246783Abstract: A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L2 of each of the implant pins into corresponding cylindrical terminals is adjustable, so that total length of the implant pin and cylindrical terminal which are press-fitted to each other matches up with the distance between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and an implant board.Type: ApplicationFiled: May 12, 2014Publication date: September 4, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Tatsuo NISHIZAWA, Shinji TADA, Yoshito KINOSHITA, Yoshinari IKEDA, Eiji MOCHIZUKI
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Publication number: 20140224862Abstract: A soldering method achieves little void and good joint condition in soldering an insulated circuit board and a semiconductor chip using a tin—high antimony solder material. A method of manufacturing a semiconductor device includes the steps of preparing a solder plate having a U-shape; mounting the solder plate on a substrate; mounting a semiconductor chip on the solder plate; fusing the solder plate in a reducing gas atmosphere; and reducing a pressure of the reducing gas atmosphere to a pressure lower than the atmospheric pressure when melting the solder plate.Type: ApplicationFiled: February 7, 2014Publication date: August 14, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takeshi MATSUSHITA, Eiji MOCHIZUKI, Tatsuo NISHIZAWA, Shunsuke SAITO
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Patent number: 8796798Abstract: An imaging module includes an imaging chip including a micro-lens guiding incident light and an imaging element in a semiconductor substrate and converting the incident light into an electric signal, and a polarizing glass chip including a polarizing filter glass having a polarizer determining a polarization direction of the incident light arranged on a transparent substrate such that the polarizer faces the micro-lens and a spacer member connected to the polarizing filter glass to adjust a gap between the polarizer and the micro-lens of the imaging chip. In the imaging module, a melt-bonding surface of the spacer member is melt-bonded to the semiconductor substrate such that the polarizer of the polarizing glass chip and the micro-lens of the imaging chip are arranged close to each other via the gap, and the imaging element and the micro-lens of the imaging chip are sealed by the polarizing glass chip.Type: GrantFiled: January 17, 2011Date of Patent: August 5, 2014Assignee: Ricoh Company, Ltd.Inventors: Daiki Minegishi, Yasuhiro Satoh, Eiji Mochizuki, Masayuki Fujishima, Hiroshi Miura
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Patent number: 8779584Abstract: A semiconductor apparatus equipped with at least one semiconductor element includes a metallic plate bonded to an upper surface of the semiconductor element and a conductor plate, bonded to the metallic plate and serving as an electric current path of the semiconductor apparatus. The conductor plate and the metallic plate are bonded to each other by laser welding at a part other than a part directly above the semiconductor element. As a result, heat damage caused by laser welding can be reduced.Type: GrantFiled: August 30, 2007Date of Patent: July 15, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Toshiyuki Yokomae, Katsumichi Ueyanagi, Eiji Mochizuki, Yoshinari Ikeda
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Patent number: 8748225Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.Type: GrantFiled: April 10, 2013Date of Patent: June 10, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Kyohei Fukuda, Eiji Mochizuki, Mitsutoshi Sawano, Takaaki Suzawa
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Patent number: 8681408Abstract: An optical scanning device includes a substrate, a frame, a torsion beam, and a cantilever. The substrate has a three-layer structure including an oxide film sandwiched between two silicon substrates. The torsion beam swingably supports a mirror portion which deflects a light beam projected from a light source. The cantilever is supported by the frame to connect to the torsion beam and applies torque to the torsion beam. The cantilever and the torsion beam are formed on the same silicon substrate. The cantilever has a thickness substantially thinner than the thickness of the torsion beam. An image forming apparatus includes the optical scanning device. An image projection device includes the optical scanning device.Type: GrantFiled: September 23, 2010Date of Patent: March 25, 2014Assignee: Ricoh Company, LimitedInventor: Eiji Mochizuki
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Publication number: 20140080262Abstract: A method for producing a semiconductor device includes solder-connecting a semiconductor chip, onto an insulating substrate including a ceramic board and having conductor layers on two surfaces thereof, with a lead-free solder; warping a radiating base such that a surface of the radiating base on a side opposite to the insulating substrate is convex; and solder-connecting the insulating substrate onto the warped radiating base with the lead-free solder so as to provide a substantially flat solder-connected radiating base.Type: ApplicationFiled: September 3, 2013Publication date: March 20, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoshitaka NISHIMURA, Akira MOROZUMI, Kazunaga OHNISHI, Eiji MOCHIZUKI, Yoshikazu TAKAHASHI