Patents by Inventor Elpida Memory, Inc.
Elpida Memory, Inc. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130175682Abstract: A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film.Type: ApplicationFiled: December 19, 2012Publication date: July 11, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130173973Abstract: A device includes memory banks, each having a plurality of memory cells with respective error data output circuits. Each of the error data output circuits outputs first to M-th (M is an integer of 2 or more) error data according to first to M-th data retrieved from first to M-th memory cell groups selected from its corresponding memory bank. A test control circuit has first error data synthesis circuits and second to (M+1)-th error data synthesis circuits, each of which synthesizes the first to M-th error data from a corresponding error data output circuit and outputs the synthesized data as first test data. Each of the error data synthesis circuits synthesizes m-th (m is an integer of from 1 to M) error data from the error data output circuits and outputs the synthesized data as (m+1)-th test data.Type: ApplicationFiled: December 19, 2012Publication date: July 4, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130173864Abstract: Disclosed herein is a device that includes a memory cell array having a plurality of pages, a row cache register, and an array control circuit. The array control circuit is configured to: select one of the pages as a selected page to form an electrical path between the selected page and the row cache register in response to a first command with a row address; cut the electrical path between the selected page and the row cache register; and form the electrical path again between the selected page and the row cache register in response to a second command without the row address.Type: ApplicationFiled: January 3, 2013Publication date: July 4, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130161733Abstract: Disclosed herein a semiconductor device, which comprises: a vertical MOS transistor that has an upper diffusion layer, and a first lower diffusion layer disposed at a lower position than the upper diffusion layer; and a first diode that has a first well isolated from the first lower diffusion layer, and a second lower diffusion layer disposed at a lower position than the upper diffusion layer and formed in the first well. A surge voltage is discharged across the second lower diffusion layer and the first well when the surge voltage is applied.Type: ApplicationFiled: December 20, 2012Publication date: June 27, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Elpida Memory, Inc.
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Publication number: 20130163303Abstract: Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer.Type: ApplicationFiled: December 20, 2012Publication date: June 27, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130162275Abstract: A semiconductor device includes a plurality of channels, a plurality of command monitor circuits provided corresponding to the plurality of channels, respectively, and a plurality of signal lines coupled in common to the plurality of command monitor circuits. Each of the plurality of command monitor circuits includes a selector configured to receive a plurality of input signals and selectively output a plurality of selected signals among the input signals, based on a first selection information, and an output circuit coupled between the selector and the plurality of signal lines, and configured to output the selected signals to the plurality of signal lines, respectively, based on a second selection information. One of the plurality of command monitor circuits is selected to output the selected signals to the plurality of signal lines while the remaining of the command monitor circuits is non selected, based on the second selection information.Type: ApplicationFiled: December 19, 2012Publication date: June 27, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130162302Abstract: Disclosed herein is a device that includes: a first circuit configured to operate on a first power voltage to produce a first set of slew rate control signals; a second circuit configured to operate on a second power voltage to produce a second set of slew rate control signals in response to the first set of slew rate control signals; and a third circuit configured to operate on the second power voltage to produce a signal at a rate that is controllable in response to the second set of slew rate control signals.Type: ApplicationFiled: December 11, 2012Publication date: June 27, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Elpida Memory, Inc.
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Publication number: 20130161738Abstract: A semiconductor device 100 includes a plurality of vertical transistors 50 provided to stand from a silicon substrate 1 and having a pillar lower diffusion layer 9 at their end portions on the silicon substrate 1 side, a metal contact plug 31 provided to stand from the silicon substrate 1 and connected to the pillar lower diffusion layer 9 of the plurality of vertical transistors 50, the plurality of vertical transistors 50 are uniformly arranged around the metal contact plug 31 and share the pillar lower diffusion layer 9 and the metal contact plug 31.Type: ApplicationFiled: December 20, 2012Publication date: June 27, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Elpida Memory, Inc.
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Publication number: 20130161827Abstract: Disclosed herein is a semiconductor chip that includes: a plurality of penetration electrodes each penetrating between main and back surfaces of the semiconductor chip, the penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and a third penetration electrode; and a wiring configured to intersect with a plurality of regions, each of the regions being defined as a region between corresponding two of the first penetration electrodes, one end of the wiring being coupled to the second penetration electrode, the other end of the wiring being coupled to the third penetration electrode.Type: ApplicationFiled: December 19, 2012Publication date: June 27, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130164909Abstract: A method of manufacturing a semiconductor device includes forming an insulating isolation portion in a groove of a substrate, forming a projection portion in which an upper portion of the insulating isolation portion projects from a principal surface of the substrate, forming a sidewall spacer covering a side surface of the projection portion and part of the principal surface of the substrate along the side surface of the projection portion, and forming a first trench in the substrate by etching the substrate using the sidewall spacer as a mask.Type: ApplicationFiled: December 14, 2012Publication date: June 27, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Elpida Memory, Inc.
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Publication number: 20130163361Abstract: A semiconductor device comprises a first pair of signal lines and a first control circuit. The first control circuit precharges each of the first pair of signal lines to a first voltage in response to a precharge signal, and changes the voltage level of each of the first pair of signal lines to a second voltage different from the first voltage when a deep power down signal is input.Type: ApplicationFiled: December 12, 2012Publication date: June 27, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Elpida Memory, Inc.
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Publication number: 20130154025Abstract: Disclosed herein is a semiconductor device that includes a first line supplied with a first voltage, a second line supplied with a second voltage, a first node, at least one first capacitor connected between the first line and the first node, at least one second capacitor connected between the node and the second line, and a protective element connected between the first node and the second line in parallel to the second capacitor.Type: ApplicationFiled: December 12, 2012Publication date: June 20, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130154096Abstract: In a manufacturing method of a barrier layer, a via hole is formed in an insulating layer that covers a conductive layer over a substrate, and then the barrier layer is formed in the via hole. The barrier layer is provided by forming a second titanium nitride film after forming a first titanium nitride film. The second titanium nitride film is formed using a method having a weak anisotropy than the first titanium nitride film.Type: ApplicationFiled: November 6, 2012Publication date: June 20, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Elpida Memory, Inc.
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Publication number: 20130153899Abstract: Disclosed herein is a device that including a first chip having first to fourth terminals and a second chip having fifth to seventh terminals. The first chip further includes a penetration electrode connected between the first and fourth electrodes and a first internal node coupled to of which an electrical potential being changed in response to an electrical potential of the first terminal. The second chip further includes a second internal node coupled to of which an electrical potential being changed in response to an electrical potential of the fifth terminal. The first internal node is electrically coupled to both the second terminal and the sixth terminal. The second internal node is electrically coupled to both the third terminal and the seventh terminal.Type: ApplicationFiled: December 19, 2012Publication date: June 20, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130154057Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.Type: ApplicationFiled: January 10, 2013Publication date: June 20, 2013Applicants: Elpida Memory, Inc, Intermolecular, Inc.Inventors: Intermolecular, Inc., Elpida Memory, Inc
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Publication number: 20130153898Abstract: Disclosed herein is a device that includes: external terminals; a first chip including a first control circuit that generates a first control signal; and a second chip stacked with the first chip. The second chip includes: a first test terminal supplied with a first test signal and being free from connecting to any one of the external terminals; a second test terminal supplied with the first test signal and coupled to one of the external terminals without connecting to any one of control circuits of the first chip; a first normal terminal supplied with the first control signal and coupled to another of the external terminals with an intervention of the first control circuit of the first chip; and a first selection circuit including first input node coupled in common to the first and second test terminals and the second input node coupled to the first normal terminal.Type: ApplicationFiled: December 19, 2012Publication date: June 20, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130154056Abstract: In a semiconductor device including a capacitor which has an upper electrode, a polycrystalline silicon layer on the upper electrode, and a metallic member on the polycrystalline silicon layer, the polycrystalline silicon layer includes germanium so that an upper portion of the polycrystalline silicon layer is lower than a lower portion thereof in a concentration of germanium.Type: ApplicationFiled: December 17, 2012Publication date: June 20, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Elpida Memory, Inc.
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Publication number: 20130155798Abstract: A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively.Type: ApplicationFiled: December 13, 2012Publication date: June 20, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Elpida Memory, Inc.
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Publication number: 20130147042Abstract: A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.Type: ApplicationFiled: December 10, 2012Publication date: June 13, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
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Publication number: 20130148412Abstract: A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending direction, while the dummy mat includes a plurality of dummy cells and arranged in a bit line extending direction at both ends of the plurality of normal memory mats. The rows of sense amplifiers are arranged between the normal memory mats and between each of the normal memory mats and each of the dummy mats. A first predetermined number of the dummy cells, the number of which is smaller than a number of the memory cells arranged along each bit line of the normal memory mats, are arranged along each bit line of the dummy mats.Type: ApplicationFiled: February 5, 2013Publication date: June 13, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Elpida Memory, Inc.