Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.

Abstract: Disclosed herein is a semiconductor chip that includes: a semiconductor chip body including a semiconductor substrate and a circuit element layer provided on a main surface of the semiconductor substrate, the circuit element layer including a plurality of circuit elements; first to fourth penetrating electrodes penetrating the semiconductor chip body; a first conductive path electrically connected between the first penetrating electrode and the second penetrating electrode without being in contact with any one of the circuit elements; a second conductive path electrically connected between the first penetrating electrode and the third penetrating electrode without being in contact with any one of the circuit elements; and a third conductive path electrically connected between the second penetrating electrode and the fourth penetrating electrode without being in contact with any one of the circuit elements.

Abstract: A device including first and second semiconductor chips, each of first and second semiconductor chips including first to M-th penetration electrodes, M being an integer equal to or greater than 3, each of the first to M-th penetration electrodes penetrating through a semiconductor substrate, and the first semiconductor chip including a first input circuit coupled to the M-th penetration electrode of the first semiconductor chip at an input node thereof, the first and second semiconductor chips being stacked with each other in which the first to M-th penetration electrodes of the second semiconductor chip are vertically arranged respectively with the first to M-th penetration electrodes of the first semiconductor chip, in which the first to (M?2)-th penetration electrodes of the second semiconductor chip are electrically coupled to the second to (M?1)-th penetration electrodes of the first semiconductor chip, respectively.

Abstract: In a semiconductor device, the thickness of an insulating film formed in a through hole is reduced, while an annular groove having an insulating material embedded therein is provided so as to ensure a sufficient total thickness of the insulator, whereby a through silicon via is provided with an insulating ring which is improved in both processability and functionality.

Abstract: A semiconductor device includes a pair of electromagnetically coupled inductors. Each of the inductors is comprised of a plurality of through electrodes which extend through a semiconductor substrate, and wires which connect the plurality of through electrodes in series.

Abstract: A semiconductor device includes a high-breakdown voltage transistor in which at least first and second vertical transistor are connected in series to each other. The first vertical transistor includes a first unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The second vertical transistor includes a second unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared.

Abstract: A method of manufacturing a semiconductor device, comprising preparing a wiring substrate and mounting a first rectangular semiconductor chip having plural of first electrodes arranged along short sides thereof on the wiring substrate. A second rectangular semiconductor chip having plural of second electrodes arranged along short sides thereof is stacked on the first semiconductor chip so that the short sides of the second semiconductor chip are perpendicular to the short sides of the first semiconductor chip and that gaps are formed between the wiring substrate and short side portions of the second semiconductor chip. The method further comprises filling the gaps with a first resin from locations near long sides of the second semiconductor chip in a direction parallel to the short sides of the second semiconductor chip. The first and the second electrodes are connected to connection pads of the wiring substrate by first and second wires, respectively.

Abstract: Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device that includes stacking a plurality of semiconductor chips to form a first chip laminated body, providing an underfill material to fill gaps between the semiconductor chips so that a fillet portion is formed around the first chip laminated body, and trimming the fillet portion to form a second chip laminated body.

Abstract: A semiconductor device includes an inverter constituted from first and second transistors connected in series between a first power supply and a second power supply and a first circuit connected between the first and second transistors which have gates coupled together. The first circuit includes a first resistance element of a positive temperature characteristic and a third transistor connected to each other in parallel. The third transistor operates at least in a region where a resistance between drain and source terminals exhibits a negative temperature characteristic.

Abstract: To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained.

Abstract: A device has a first substrate having a first surface; a first electrode pad arranged on the first surface of the first substrate; a first insulator film provided on the first surface of the first substrate so that the first electrode pad is exposed; a first bump electrode provided on the first electrode pad and having a first diameter; and a second bump electrode provided on the first insulator film and having a second diameter smaller than the first diameter.

Abstract: A semiconductor device includes a semiconductor substrate having first and second regions, a first pillar transistor, and a second pillar transistor, wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar, wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar, wherein the first gate electrode is different in height from the second gate electrode, and the first and second pillar transistors form a CMOS device.

Abstract: Disclosed herein is a device that includes a first semiconductor chip outputting a read command and a clock signal, a plurality of second semiconductor chips stacked to the first semiconductor chip, and a signal path electrically connected between the first and second semiconductor chips. Each of the second semiconductor chips performs a read operation to read out a data signal stored therein in response to the read command. Each of the second semiconductor chips includes a counter circuit performing a count operation in response to the clock signal to generate a count signal, and an output control circuit outputs the data signal to the signal path when the count signal indicates a predetermined value. The predetermined values of the second semiconductor chips are different from one another.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.

Abstract: A method for manufacturing a semiconductor device includes at least forming a lower electrode comprising titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide as a primary constituent on the lower electrode, forming a first protective film comprising a titanium compound on the dielectric film, and forming an upper electrode comprising titanium nitride on the first protective film. The method can include a step of forming a second protective film on the lower electrode before the step of forming the dielectric film on the lower electrode.

Abstract: A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.

Abstract: Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal.