Patents by Inventor Elpida Memory, Inc.

Elpida Memory, Inc. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130080826
    Abstract: Disclosed herein is a semiconductor device that includes a verification circuit and an error processing circuit. the verification circuit verifies second bits of an external command to generate the verification result signal. The error processing circuit supplies a follow-up signal to a bank control circuit after a lapse of a first period and a second period when the verification result signal indicates a fail state during a write operation. The first period corresponds to a write latency indicating a period between when a write command is generated and when a data associated with the write command is supplied from outside. The second period corresponds to a write recovery latency indicating a period between when the bank control circuit issues a write execution signal to start writing the data to memory cells and when the write operation is completed.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 28, 2013
    Applicant: Elpida Memory, INC.
    Inventor: Elpida Memory, INC.
  • Publication number: 20130071991
    Abstract: A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO2) on the first TiN electrode; depositing a dielectric material on the first layer of titanium dioxide; and depositing a second TiN electrode on the dielectric material.
    Type: Application
    Filed: November 14, 2012
    Publication date: March 21, 2013
    Applicants: ELPIDA MEMORY, INC, INTERMOLECULAR, INC.
    Inventors: Intermolecular, Inc., Elpida Memory, Inc.
  • Publication number: 20130058180
    Abstract: A system includes a first circuit and a second circuit that are constituted by a semiconductor device, the second circuit controlling the first circuit. The first circuit includes an interface unit that performs communication with the second circuit, a plurality of sense amplifiers including a first sense amplifier, each of the plurality of sense amplifiers performing communication with the interface unit, a first global bit line, a dummy global bit line, a plurality of first memory blocks, each of the first memory blocks including a first hierarchy switch that is connected to the first global bit line, a dummy memory block including a dummy hierarchy switch that is connected to the dummy global bit line, and a first dummy local bit line connected to the dummy global bit line, and a control circuit that controls the first hierarchy switches and the dummy hierarchy switch.
    Type: Application
    Filed: October 31, 2012
    Publication date: March 7, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Elpida Memory, Inc.
  • Publication number: 20130056851
    Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.
    Type: Application
    Filed: October 31, 2012
    Publication date: March 7, 2013
    Applicants: ELPIDA MEMORY, INC, INTERMOLECULAR, INC.
    Inventors: Intermolecular, Inc., Elpida Memory, Inc.
  • Publication number: 20130043596
    Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.
    Type: Application
    Filed: October 19, 2012
    Publication date: February 21, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Elpida Memory, Inc.
  • Publication number: 20130045582
    Abstract: A capacitor insulating film may include, but is not limited to, strontium, titanium, and oxygen. The capacitor insulating film has a ratio of a spectrum intensity of (200) crystal face of the capacitor insulating film to a spectrum intensity of (111) crystal face of the capacitor insulating film in the range of 1.0 to 2.3. Each of the spectrum intensities of (200) crystal face and (111) crystal face is measured by an X-ray diffraction method.
    Type: Application
    Filed: October 25, 2012
    Publication date: February 21, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Elpida Memory, Inc.
  • Publication number: 20130039136
    Abstract: A semiconductor device includes a memory cell, a first bit line coupled to the memory cell, a second bit line, a first sense amplifier circuit including first and second transistors, the first transistor including a gate coupled to the first bit line, and the first and second transistors are coupled in series between the second bit line and a first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and supply a control signal to a gate of the second transistor.
    Type: Application
    Filed: October 16, 2012
    Publication date: February 14, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Elpida Memory, Inc.
  • Publication number: 20130039118
    Abstract: A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence, and the second voltage has a temperature dependence opposite to that of a forward voltage of the diode. The control circuit detects a resistance state of the memory element in accordance with a change in current flowing in the memory cell in a state where the first/second voltage is applied to the first/second in a read operation of the memory cell.
    Type: Application
    Filed: October 10, 2012
    Publication date: February 14, 2013
    Applicant: ELPIDA MEMORY INC.
    Inventor: Elpida Memory Inc.
  • Publication number: 20130026652
    Abstract: A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip 2, semiconductor chip 3a stacked on substrate 4 together with semiconductor chip 2, and having a foot print larger than semiconductor chip 2, through electrode 22 extending through semiconductor chip 2 only in a central portion of semiconductor chip 2, through electrode 32 extending through semiconductor chip 3a at a position facing to through electrode 22, and conduction bump 7b arranged between through electrode 22 and through electrode 32, and conductively connecting through electrode 22 with through electrode 32.
    Type: Application
    Filed: October 1, 2012
    Publication date: January 31, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Elpida Memory, Inc.
  • Publication number: 20130021016
    Abstract: In accordance with a bandgap circuit and a method of starting the bandgap circuit, a start signal is continuously supplied to a differential amplifier circuit to start up the differential amplifier circuit that controls a bandgap core circuit until the differential amplifier circuit has started up, and then the supply of the start signal to the differential amplifier circuit is discontinued after the differential amplifier circuit has started up.
    Type: Application
    Filed: September 27, 2012
    Publication date: January 24, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Elpida Memory, Inc.