Patents by Inventor En-Hsiang Yeh
En-Hsiang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230127322Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: ApplicationFiled: December 21, 2022Publication date: April 27, 2023Inventors: WEN-SHENG CHEN, AN-HSUN LO, EN-HSIANG YEH, TZU-JIN YEH
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Publication number: 20230125874Abstract: A power amplifier structure includes at least one power amplifier circuit. The power amplifier circuit includes a transistor of a first type connected in series with a transistor of a second type connected between the same voltage supply. In a non-limiting nonexclusive example, an n-type transistor is connected in series with a p-type transistor connected between Vdd. The power amplifier structure can include two amplifier circuits configured in a differential amplifier structure. The differential amplifier structure includes two amplifier circuits operably connected in parallel between the same voltage supply.Type: ApplicationFiled: March 15, 2022Publication date: April 27, 2023Inventors: Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20230112936Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.Type: ApplicationFiled: December 14, 2022Publication date: April 13, 2023Inventors: Garming LIANG, Simon CHAI, Tzu-Jin YEH, En-Hsiang YEH, Wen-Sheng CHEN
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Patent number: 11569164Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: GrantFiled: May 21, 2020Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh
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Patent number: 11558019Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.Type: GrantFiled: November 4, 2019Date of Patent: January 17, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Garming Liang, Simon Chai, Tzu-Jin Yeh, En-Hsiang Yeh, Wen-Sheng Chen
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Patent number: 11532868Abstract: An antenna apparatus comprises a semiconductor die in a molding compound layer, a first through via is between a sidewall of the semiconductor die and a sidewall of the molding compound layer and an antenna structure over the molding compound layer, wherein a first portion of the antenna structure is directly over a top surface of the semiconductor die and a second portion of the antenna structure is directly over a top surface of the first through via.Type: GrantFiled: March 23, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lai Wei Chih, Monsen Liu, En-Hsiang Yeh, Chuei-Tang Wang, Chen-Hua Yu
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Publication number: 20220385251Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: An-Hsun LO, Wen-Sheng CHEN, En-Hsiang YEH, Tzu-Jin YEH
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Patent number: 11456710Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: GrantFiled: October 5, 2020Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: An-Hsun Lo, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Patent number: 11456711Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.Type: GrantFiled: August 31, 2020Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: En-Hsiang Yeh, Wen-Sheng Chen, Chia-Ming Liang, Chung-Ho Chai, Zong-You Li, Tzu-Jin Yeh
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Patent number: 11329647Abstract: In a communication system, a communication terminal device transmits and receives RF signals frequently. Subsequent to an antenna of the communication terminal device, the communication terminal device includes a radio frequency switch (also referred to as transmit/receive (T/R) switch) that switches between two states at a high frequency, where one state is for receiving RF signal and other state for transmitting RF signal. In the exemplary embodiments of the disclosure, a complementary metal-oxide-semiconductor (CMOS) switch is provided, where the CMOS switch is deigned to have a high reliability by coupling a body of a transistor of the CMOS switch to a bias voltage through a switch, where the insertion loss and isolation are improved for the operation of the CMOS switch.Type: GrantFiled: October 29, 2019Date of Patent: May 10, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Garming Liang, En-Hsiang Yeh
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Publication number: 20220069779Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: En-Hsiang Yeh, Wen-Sheng Chen, Chia-Ming Liang, Chung-Ho Chai, Zong-You Li, Tzu-Jin Yeh
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Publication number: 20210328347Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: Monsen Liu, Lai Wei Chih, Chung-Hao Tsai, Jeng-Shien Hsieh, En-Hsiang Yeh, Chuei-Tang Wang
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Patent number: 11050153Abstract: A method includes placing a device die and a pre-formed dielectric block over a first carrier, encapsulating the device die and the pre-formed dielectric block in an encapsulating material, grinding a top side of the encapsulating material to expose the top side of the pre-formed dielectric block, removing the carrier from the encapsulating material, the pre-formed dielectric block, and the device die to reveal a bottom side of the pre-formed dielectric block, and forming a ground panel, a feeding line, and a patch on the encapsulating material. The ground panel, the feeding line, the patch, and the pre-formed dielectric block form a patch antenna.Type: GrantFiled: April 22, 2019Date of Patent: June 29, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Monsen Liu, Lai Wei Chih, Chung-Hao Tsai, Jeng-Shien Hsieh, En-Hsiang Yeh, Chuei-Tang Wang
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Publication number: 20210126631Abstract: In a communication system, a communication terminal device transmits and receives RF signals frequently. Subsequent to an antenna of the communication terminal device, the communication terminal device includes a radio frequency switch (also referred to as transmit/receive (T/R) switch) that switches between two states at a high frequency, where one state is for receiving RF signal and other state for transmitting RF signal. In the exemplary embodiments of the disclosure, a complementary metal-oxide-semiconductor (CMOS) switch is provided, where the CMOS switch is deigned to have a high reliability by coupling a body of a transistor of the CMOS switch to a bias voltage through a switch, where the insertion loss and isolation are improved for the operation of the CMOS switch.Type: ApplicationFiled: October 29, 2019Publication date: April 29, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Garming Liang, En-Hsiang Yeh
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Patent number: 10985618Abstract: A wireless transmitter includes a an amplifier; and a switchable transformer, coupled to the amplifier, wherein the amplifier is configured to be coupled to the switchable transformer in first and second configurations, wherein the first configuration causes the amplifier to provide a first output impedance to the switchable transformer, and wherein the second configuration causes the amplifier to provide a second output impedance to the switchable transformer, the first and second output impedances being different from each other.Type: GrantFiled: October 28, 2019Date of Patent: April 20, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20210028811Abstract: A method includes switching a receiver path network of a front-end module to a first matching mode in a receive mode. The method further includes switching a transmitter path network of the front-end module to a first resonance mode in the receive mode. The method further includes switching the transmitter path network to a second matching mode in a transmit mode. The method further includes switching the receiver path network to a second resonance mode in the transmit mode.Type: ApplicationFiled: October 8, 2020Publication date: January 28, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: En-Hsiang YEH, Monsen LIU, Chuei-Tang WANG
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Publication number: 20210021240Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: An-Hsun LO, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Patent number: 10804953Abstract: A method includes (a) switching a receiver path network of a front end module to a first matching mode in a receive mode. The method further includes (b) switching a transmitter path network of the front end module to a first resonance mode in the receive mode. The method further includes (c) switching the transmitter path network to a second matching mode in a transmit mode. The method further includes (d) switching the receiver path network to a second resonance mode in the transmit mode.Type: GrantFiled: October 28, 2019Date of Patent: October 13, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: En-Hsiang Yeh, Monsen Liu, Chuei-Tang Wang
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Patent number: 10797655Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: GrantFiled: November 4, 2016Date of Patent: October 6, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: An-Hsun Lo, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20200279808Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: ApplicationFiled: May 21, 2020Publication date: September 3, 2020Inventors: WEN-SHENG CHEN, AN-HSUN LO, EN-HSIANG YEH, TZU-JIN YEH