Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.

Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.

Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.

Abstract: An antenna apparatus comprises a semiconductor die in a molding compound layer, a first through via is between a sidewall of the semiconductor die and a sidewall of the molding compound layer and an antenna structure over the molding compound layer, wherein a first portion of the antenna structure is directly over a top surface of the semiconductor die and a second portion of the antenna structure is directly over a top surface of the first through via.

Abstract: An amplifying unit includes a converter and a feedback mechanism. The converter has a supply input coupled to a supply node. The converter further has an input terminal configured to receive an input signal. The converter is configured to amplify the input signal from the input terminal to generate an output signal. The feedback mechanism is coupled to the input terminal of the converter and is configured to cause a constant bias current to flow from the supply node through the converter based on the input signal.

Abstract: An antenna apparatus comprises a semiconductor die embedded in and adjacent to a first side of a molding compound layer, a plurality of first interconnects formed on the first side of the molding compound layer, wherein the plurality of first interconnects are electrically connected the semiconductor die and an antenna structure formed on a second side of the molding compound layer, wherein the antenna structure is electrically connected to the semiconductor die through a via connected between the plurality of first interconnects and the antenna structure.

Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first trans conductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.

Abstract: A wireless transmitter includes a an amplifier; and a switchable transformer, coupled to the amplifier, wherein the amplifier is configured to be coupled to the switchable transformer in first and second configurations, wherein the first configuration causes the amplifier to provide a first output impedance to the switchable transformer, and wherein the second configuration causes the amplifier to provide a second output impedance to the switchable transformer, the first and second output impedances being different from each other.

Abstract: A tunable three-dimensional (3D) inductor comprises a plurality of vias arranged with spacing among them, a plurality of interconnects in a metal layer, wherein the plurality of interconnects connect the plurality of vias on one end, and a plurality of tunable wires that connects to the plurality of vias on the other end to form the 3D inductor. The physical configuration and inductance value of the 3D inductor are adjustable by tuning the plurality of tunable wires during manufacturing process.

Abstract: An energy harvesting device comprises a semiconductor device, and a first magnet core. The semiconductor device, disposed in a housing, includes planar inductors. The first magnet core, having a first surface over the planar inductors, is configured to move with respect to the semiconductor device in a first direction that reduces a first vertical distance between the plane and the first surface.

Abstract: A method making a three-dimensional inductor, the method including: forming a plurality of vias in a substrate or a molding compound, wherein the vias are arranged with spacings among them; forming a metal layer having interconnects, wherein the interconnects of the metal layer connect the plurality of vias on one end of the vias; forming a plurality of wires to connect the plurality of vias on the other end of the vias to form the 3D inductor; and tuning one or more of the plurality of wires to adjust a physical configuration and inductance value of the 3D inductor.

Abstract: A device is disclosed that includes a first gain stage and a first amplifier. The first gain stage is configured to generate a first signal according to a first input signal, and to multiply the first signal and the first input signal, to generate a second signal at a first output terminal, in which the first signal is associated with the even order signal components of the first input signal. The first amplifier is configured to amplify the first input signal to generate a third signal at the first output terminal, in order to output a first output signal with the first gain stage, in which the first output signal is the sum of the second signal and the third signal.

Abstract: A device is disclosed that includes a first gain stage and a first amplifier. The first gain stage is configured to generate a first signal according to a first input signal, and to multiply the first signal and the first input signal, to generate a second signal at a first output terminal, in which the first signal is associated with the even order signal components of the first input signal. The first amplifier is configured to amplify the first input signal to generate a third signal at the first output terminal, in order to output a first output signal with the first gain stage, in which the first output signal is the sum of the second signal and the third signal.

Abstract: An antenna apparatus comprises a semiconductor die embedded in and adjacent to a first side of a molding compound layer, a plurality of first interconnects formed on the first side of the molding compound layer, wherein the plurality of first interconnects are electrically connected the semiconductor die and an antenna structure formed on a second side of the molding compound layer, wherein the antenna structure is electrically connected to the semiconductor die through a via connected between the plurality of first interconnects and the antenna structure.

Abstract: A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line.

Abstract: Methods and apparatus are disclosed for a package or a package-on-package (PoP) device. An IC package or a PoP device may comprise an electrical path connecting a die and a decoupling capacitor, wherein the electrical path may have a width in a range from about 8 um to about 44 um and a length in a range from about 10 um to about 650 um. The decoupling capacitor and the die may be contained in a same package, or at different packages within a PoP device, connected by contact pads, redistribution layers (RDLs), and connectors.

Abstract: A voltage-to-current converter is disclosed. The voltage to current converter includes a converter circuit having an input node, an amplified signal node and an output. The input node is configured to receive a sinusoidal voltage signal and the output is configured to provide a half-wave current signal. A transistor having a gate, a source, and a drain is coupled to the input node. The input node is coupled to one of the source or the drain. The amplified signal node is coupled to the gate. A process tracking stabilizer is coupled to the transistor at the source or the drain not coupled to the input node. The process tracking stabilizer is configured to generate a control voltage for the transistor. The control voltage is configured to maintain a predetermined non-zero voltage at the input node of the converter circuit during a negative cycle of the sinusoidal voltage signal.

Abstract: An energy harvesting device comprises a semiconductor device, and a first magnet core. The semiconductor device, disposed in a housing, includes planar inductors. The first magnet core, having a first surface over the planar inductors, is configured to move with respect to the semiconductor device in a first direction that reduces a first vertical distance between the plane and the first surface.

Abstract: An antenna apparatus comprises a semiconductor die comprising a plurality of active circuits, a molding layer formed over the semiconductor die, wherein the semiconductor die and the molding layer form a fan-out package, a first dielectric layer formed on a first side of the semiconductor die over the molding compound layer, a first redistribution layer formed in the first dielectric layer and an antenna structure formed above the semiconductor die and coupled to the plurality of active circuits through the first redistribution layer.

Abstract: An energy harvesting device comprises a semiconductor device, a first magnet core, and at least one second magnet core. The semiconductor device, disposed in a housing, includes a plurality of first sensors and a plurality of second sensors. The first magnet core, disposed over the semiconductor device, is configured to establish a magnetic field between the first sensors and move with respect to the semiconductor device. The at least one second magnet core, disposed between an inner wall of the housing and the semiconductor device, is configured to establish a magnetic field between the second sensors and move with respect to the semiconductor device.