Patents by Inventor En-Hsiang Yeh

En-Hsiang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8975726
    Abstract: A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu-Hsien Chen, Chih-Hua Chen, En-Hsiang Yeh, Monsen Liu, Chen-Shien Chen
  • Publication number: 20150042438
    Abstract: A tunable three-dimensional (3D) inductor comprises a plurality of vias arranged with spacing among them, a plurality of interconnects in a metal layer, wherein the plurality of interconnects connect the plurality of vias on one end, and a plurality of tunable wires that connects to the plurality of vias on the other end to form the 3D inductor. The physical configuration and inductance value of the 3D inductor are adjustable by tuning the plurality of tunable wires during manufacturing process.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Monsen Liu, Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20150011083
    Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.
    Type: Application
    Filed: September 19, 2014
    Publication date: January 8, 2015
    Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
  • Patent number: 8916979
    Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
  • Publication number: 20140185264
    Abstract: Methods and apparatus are disclosed for a package or a package-on-package (PoP) device. An IC package or a PoP device may comprise an electrical path connecting a die and a decoupling capacitor, wherein the electrical path may have a width in a range from about 8 um to about 44 um and a length in a range from about 10 um to about 650 um. The decoupling capacitor and the die may be contained in a same package, or at different packages within a PoP device, connected by contact pads, redistribution layers (RDLs), and connectors.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu-Hsien Chen, Chih-Hua Chen, En-Hsiang Yeh, Monsen Liu, Chen-Shien Chen
  • Publication number: 20140183754
    Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.
    Type: Application
    Filed: February 7, 2013
    Publication date: July 3, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
  • Publication number: 20140168014
    Abstract: An antenna apparatus comprises a semiconductor die comprising a plurality of active circuits, a molding layer formed over the semiconductor die, wherein the semiconductor die and the molding layer form a fan-out package, a first dielectric layer formed on a first side of the semiconductor die over the molding compound layer, a first redistribution layer formed in the first dielectric layer and an antenna structure formed above the semiconductor die and coupled to the plurality of active circuits through the first redistribution layer.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lai Wei Chih, Monsen Liu, En-Hsiang Yeh, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20140152509
    Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Monsen Liu, Lai Wei Chih, Chung-Hao Tsai, Jeng-Shien Hsieh, En-Hsiang Yeh, Chuei-Tang Wang
  • Publication number: 20140128009
    Abstract: A front end module includes a transmitter path network coupled to an antenna and a transmitter, and includes a first selectable matching network. The front end module further includes a receiver path network coupled to the antenna and a receiver. The receiver path network is a second selectable matching network.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: En-Hsiang YEH, Monsen LIU, Chuei-Tang WANG
  • Publication number: 20140103488
    Abstract: A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsu-Hsien Chen, Chih-Hua Chen, En-Hsiang Yeh, Monsen Liu, Chen-Shien Chen
  • Patent number: 8085087
    Abstract: A switched capacitor circuit includes a positive side capacitor coupled to a first positive side node; a first positive side switch element for selectively coupling the first positive side node to a second node according to a first control signal; and a precharge circuit coupled to the first positive side node for precharging the first positive side node to a precharge voltage for a predetermined time when the first positive side switch element is switched off according to the first control signal, and then for charging the first positive side node to a charge voltage until the first positive side switch element is switched on according to the first control signal. By rapidly precharging the first positive side node, the clock feedthrough effect is eliminated and the locking period of the VCO is shortened. Afterwards by charging the first positive side node, the phase noise of the VCO is minimized.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: December 27, 2011
    Assignee: Mediatek Inc.
    Inventor: En-Hsiang Yeh
  • Patent number: 7957698
    Abstract: A calibration circuit for calibrating an output level of a demodulator includes a test signal generator, an RSSI module and a calibration module. The test signal generator generates a test signal, and the RSSI module detects the test signal to generate a control signal, wherein the control signal controls the demodulator to process the test signal to generate a determined output signal. The calibration module then calibrates the RSSI module according to the output signal in order to calibrate the output level of the demodulator. When the control signal is utilized to selectively enable or disable a soft-mute function of the demodulator, the calibration module can be utilized to calibrate or determine the soft-mute function of the demodulator.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: June 7, 2011
    Assignee: Mediatek Inc.
    Inventors: Tsung-Ling Li, Hsiang-Hui Chang, Chia-Huang Fu, En-Hsiang Yeh, Hsueh-Kun Liao, Chieh-Hung Chen
  • Publication number: 20100019826
    Abstract: A switched capacitor circuit includes a positive side capacitor coupled to a first positive side node; a first positive side switch element for selectively coupling the first positive side node to a second node according to a first control signal; and a precharge circuit coupled to the first positive side node for precharging the first positive side node to a precharge voltage for a predetermined time when the first positive side switch element is switched off according to the first control signal, and then for charging the first positive side node to a charge voltage until the first positive side switch element is switched on according to the first control signal. By rapidly precharging the first positive side node, the clock feedthrough effect is eliminated and the locking period of the VCO is shortened. Afterwards by charging the first positive side node, the phase noise of the VCO is minimized.
    Type: Application
    Filed: October 9, 2009
    Publication date: January 28, 2010
    Inventor: En-Hsiang Yeh
  • Patent number: 7622980
    Abstract: A switched capacitor circuit includes a positive side capacitor coupled to a first positive side node; a first positive side switch element for selectively coupling the first positive side node to a second node according to a first control signal; and a precharge circuit coupled to the first positive side node for precharging the first positive side node to a precharge voltage for a predetermined time when the first positive side switch element is switched off according to the first control signal, and then for charging the first positive side node to a charge voltage until the first positive side switch element is switched on according to the first control signal. By rapidly precharging the first positive side node, the clock feedthrough effect is eliminated and the locking period of the VCO is shortened. Afterwards by charging the first positive side node, the phase noise of the VCO is minimized.
    Type: Grant
    Filed: September 3, 2006
    Date of Patent: November 24, 2009
    Assignee: MediaTek Inc.
    Inventor: En-Hsiang Yeh
  • Publication number: 20090233566
    Abstract: A calibration circuit for calibrating an output level of a demodulator includes a test signal generator, an RSSI module and a calibration module. The test signal generator generates a test signal, and the RSSI module detects the test signal to generate a control signal, wherein the control signal controls the demodulator to process the test signal to generate a determined output signal. The calibration module then calibrates the RSSI module according to the output signal in order to calibrate the output level of the demodulator. When the control signal is utilized to selectively enable or disable a soft-mute function of the demodulator, the calibration module can be utilized to calibrate or determine the soft-mute function of the demodulator.
    Type: Application
    Filed: March 11, 2008
    Publication date: September 17, 2009
    Inventors: Tsung-Ling Li, Hsiang-Hui Chang, Chia-Huang Fu, En-Hsiang Yeh, Hsueh-Kun Liao, Chieh-Hung Chen
  • Patent number: 7446604
    Abstract: A multi-band low noise amplifier capable of operating in a plurality of band modes includes a plurality of input amplifiers respectively corresponding to the plurality of band modes and a single output amplifier. Each input amplifier includes a receiving port for receiving a corresponding input signal in one of the plurality of band modes. The single output amplifier includes at least one port coupled to the plurality of input amplifiers and an output port for outputting a signal processed by the single output amplifier.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: November 4, 2008
    Assignee: Mediatek Inc.
    Inventor: En-Hsiang Yeh
  • Patent number: 7332951
    Abstract: A switched capacitor circuit includes a positive side capacitor coupled to a first positive side node; a first positive side switch element for selectively coupling the first positive side node to a second node according to a first control signal; and precharge circuit coupled to the first positive side node for precharging the first positive side node to a precharge voltage for a predetermined time when the first positive side switch element is switched off according to the first control signal, and then for charging the first positive side node to a charge voltage until the first positive side switch element is switched on according to the first control signal. By rapidly precharging the first positive side node, the clock feedthrough effect is eliminated and the locking period of the VCO is shortened. Afterwards by charging the first positive side node, the phase noise of the VCO is minimized.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: February 19, 2008
    Assignee: Mediatek Incorporation
    Inventor: En-Hsiang Yeh
  • Publication number: 20070093230
    Abstract: A multi-band low noise amplifier capable of operating in a plurality of band modes includes a plurality of input amplifiers respectively corresponding to the plurality of band modes and a single output amplifier. Each input amplifier includes a receiving port for receiving a corresponding input signal in one of the plurality of band modes. The single output amplifier includes at least one port coupled to the plurality of input amplifiers and an output port for outputting a signal processed by the single output amplifier.
    Type: Application
    Filed: December 7, 2006
    Publication date: April 26, 2007
    Inventor: En-Hsiang Yeh
  • Patent number: 7187239
    Abstract: A multi-band low noise amplifier capable of operating in a plurality of band modes includes a plurality of input amplifiers respectively corresponding to the plurality of band modes and an output amplifier. Each input amplifier includes a receiving port for receiving a corresponding input signal in the band mode. The output amplifier includes at least a lowest-impedance port being a lowest-impedance node of the multi-band low noise amplifier and an output port for outputting the input signal processed by the output amplifier. The output amplifier is coupled to the plurality of input amplifiers at the lowest-impedance port.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: March 6, 2007
    Assignee: Mediatek Incorporation
    Inventor: En-Hsiang Yeh
  • Publication number: 20060290406
    Abstract: A switched capacitor circuit includes a positive side capacitor coupled to a first positive side node; a first positive side switch element for selectively coupling the first positive side node to a second node according to a first control signal; and a precharge circuit coupled to the first positive side node for precharging the first positive side node to a precharge voltage for a predetermined time when the first positive side switch element is switched off according to the first control signal, and then for charging the first positive side node to a charge voltage until the first positive side switch element is switched on according to the first control signal. By rapidly precharging the first positive side node, the clock feedthrough effect is eliminated and the locking period of the VCO is shortened. Afterwards by charging the first positive side node, the phase noise of the VCO is minimized.
    Type: Application
    Filed: September 3, 2006
    Publication date: December 28, 2006
    Inventor: En-Hsiang Yeh