Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Abstract: Devices, systems, and methods for timing elements of memory read and write operations are disclosed. A device may include a first DQ pin, a second DQ pin, and an output circuit. The output circuit may be configured to provide: a first signal at the first DQ pin and a second signal at the second DQ pin, based on the timing pattern. In some embodiments, based on the timing pattern, the output circuit may be configure to delay the first signal relative to the second signal such that rising and falling edges of the first signal do not coincide with rising and falling edges of the second signal. In these or other embodiments, the device may further include a mode register, wherein a slew rate of the first signal is based at least in part on a value of the mode register. Associated systems and methods are also disclosed.

Abstract: Systems, apparatuses, and methods for test devices having parallel impedances to reduce measurement input impedance are disclosed. An apparatus includes a test input terminal, a measurement output terminal, a reference voltage potential node, and a parallel resistor. The test input terminal is configured to electrically connect to a signal output terminal of a signal generator. The test input terminal is configured to receive a test signal from the signal generator via the signal output terminal. The measurement output terminal electrically connects to a measurement input terminal of an electrical measurement instrument. The parallel resistor is electrically connected from the measurement output terminal to the reference voltage potential node. A system includes the apparatus and the electrical measurement instrument. A method includes providing a test signal to the test device, verifying the test signal using the electrical measurement instrument, and providing the test signal to a device under test.

Abstract: Devices, systems, and methods for timing elements of memory read and write operations are disclosed. A device may include a first DQ pin, a second DQ pin, and an output circuit. The output circuit may be configured to provide: a first signal at the first DQ pin and a second signal at the second DQ pin, based on the timing pattern. In some embodiments, based on the timing pattern, the output circuit may be configure to delay the first signal relative to the second signal such that rising and falling edges of the first signal do not coincide with rising and falling edges of the second signal. In these or other embodiments, the device may further include a mode register, wherein a slew rate of the first signal is based at least in part on a value of the mode register. Associated systems and methods are also disclosed.

Abstract: Apparatuses for characterizing system channels and associated methods and systems are disclosed. In one embodiment, a tester is coupled to an adaptor configured to plug into a CPU socket of a system platform (e.g., a motherboard). The motherboard includes a memory socket that is connected to the CPU socket through system channels. The adaptor may include a connector configured to physically and electrically engage with the CPU socket, an interface configured to receive test signals from the tester, and circuitry configured to internally route the test signals to the connector. The adaptor, if plugged into the CPU socket, can facilitate the tester to directly assess signal transfer characteristics of the system channels. Accordingly, the tester can determine optimum operating parameters for the memory device in view of the system channel characteristics.

Abstract: Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

Abstract: Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.

Abstract: Memory devices and systems with per pin input/output termination and driver impedance calibration capabilities, and associated methods, are disclosed herein. In one embodiment, a device apparatus includes circuitry dedicated to an individual DQ pin of the device apparatus. The circuitry can be configured to (i) generate, at least in part, a voltage at the DQ pin based, at least in part, on an impedance internal to a host device electrically connected to the device apparatus and (ii) compare the voltage to a target voltage. Based, at least in part, on the comparison, the circuitry can be configured to adjust a resistance of an output driver and/or a termination circuit of the device apparatus that correspond to the DQ pin to adjust the impedance of the output driver and/or termination circuit to match an impedance associated with a corresponding input/output pin of the host device.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

Abstract: Memory devices and systems with per pin input/output termination and driver impedance calibration capabilities, and associated methods, are disclosed herein. In one embodiment, a device apparatus includes circuitry dedicated to an individual DQ pin of the device apparatus. The circuitry can be configured to (i) generate, at least in part, a voltage at the DQ pin based, at least in part, on an impedance internal to a host device electrically connected to the device apparatus and (ii) compare the voltage to a target voltage. Based, at least in part, on the comparison, the circuitry can be configured to adjust a resistance of an output driver and/or a termination circuit of the device apparatus that correspond to the DQ pin to adjust the impedance of the output driver and/or termination circuit to match an impedance associated with a corresponding input/output pin of the host device.

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

Abstract: Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.

Abstract: Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

Abstract: A method for equalizing command/address signals in a memory device includes receiving a status of a termination pin for a memory device and automatically performing equalization on signals received on a command/address bus channel of the memory device based on the status. An apparatus for equalizing command/address signals in a memory device includes an input buffer circuit configured to receive the signals from a command/address bus channel. The apparatus also includes a filter circuit configured to automatically perform equalization on the signals based on a status of a termination pin.

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

Abstract: A method of operating an oscilloscope is disclosed. The method comprises providing a bit stream comprising pseudo-random data to an oscilloscope across a data path characterized by sufficient signal degradation to prevent the oscilloscope from reliably triggering a sweep of an eye pattern based on receiving the pseudo-random data; inserting a predetermined sequence of bits into the bit stream at predetermined periodic intervals to open the eye pattern sufficiently during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye pattern; and generating the eye pattern based at least in part on the pseudo-random data and excluding the predetermined sequence of bits from the sweep of the eye pattern. Oscilloscopes configured to trigger according to a predetermined system of bits at predetermined intervals are also disclosed.