Abstract: In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a substrate including a plurality of access transistors, and a plurality of storage capacitors corresponding uniquely to the plurality of access transistors, each storage capacitor being formed in a plurality of semiconductor manufacturing process metal layers adjacent the substrate.

Abstract: In one embodiment, a memory is provided that includes: a plurality of memory cells arranged in columns, each column coupled to a corresponding bit line; a sense amplifier adapted to sense the voltage on a pair of the bit lines to determine a binary state of an accessed memory cell coupled to a first one of the bit lines in the pair; and a first trim capacitor having a first terminal directly coupled to one of the bit lines in the pair, the first trim capacitor having an opposing second terminal coupled to a first trim capacitor signal, the memory being adapted to change a voltage of the first trim capacitor signal while the sense amplifier senses the voltage to determine the binary state of the accessed memory cell.

Abstract: In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.

Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal layer capacitor includes a first plate coupled to the floating gate and a second plate separated from the first plate by a fringe capacitance junction.

Abstract: A one-time-programmable memory cell uses two complementary antifuses that are programmed in a complementary fashion such that only one of the two complementary antifuses is stressed by a programming voltage. The programming voltage stress one a particular one of the complementary antifuses indicates a logical state of the memory cell. For example, a logical high state may correspond to a first one of the complementary antifuses being stressed whereas a logical low state may correspond to the stressing of the remaining one of the complementary antifuses.

Abstract: An imaging device includes a plurality of photo-diodes arranged in a plurality of columns on a single Complementary Metal Oxide Semiconductor (CMOS) substrate. A plurality of analog-to-digital converters (ADCs) corresponding to the plurality of columns of photo-diodes are arranged on the substrate, with each ADC having an input coupled to outputs of the photo-diodes in the corresponding column. Parallel processing of the data streams produced by the multiple ADCs improves the bandwidth of the imaging device. The ADCs have one or more capacitors based on a reference capacitor that are configured so that the corresponding capacitors for different ADCs are substantially equal across the CMOS substrate. As such, image variation and streaking across the columns of photo-diodes is minimized or eliminated. The reference capacitors of the ADCs are above a minimum capacitance value, determined by a maximum variation of the reference capacitors across the substrate.

Abstract: Data encoding system and method for implementing robust non-volatile memories. A data bit is stored using two memory cells. The data bit is represented by setting a voltage level of a first memory cell to a first voltage level and setting a voltage level of a second memory cell to a second voltage level. In one embodiment, the first voltage level and the second voltage level are of opposite polarity. In one embodiment, to store a data bit having the value “0,” the first memory cell is set to a first voltage level and the second memory cell is set to a second voltage level of opposite polarity to the first voltage level, and to store a data bit having the value “1,” the first memory cell is set to a third voltage level and the second memory cell is set to a fourth voltage level of opposite polarity to the third voltage level.

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can include selectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract: Data encoding system and method for implementing robust non-volatile memories. A data bit is stored using two memory cells. The data bit is represented by setting a voltage level of a first memory cell to a first voltage level and setting a voltage level of a second memory cell to a second voltage level. In one embodiment, the first voltage level and the second voltage level are of opposite polarity. In one embodiment, to store a data bit having the value “0,” the first memory cell is set to a first voltage level and the second memory cell is set to a second voltage level of opposite polarity to the first voltage level, and to store a data bit having the value “1,” the first memory cell is set to a third voltage level and the second memory cell is set to a fourth voltage level of opposite polarity to the third voltage level.

Abstract: In one embodiment, a CAM is provided that includes; a plurality of memory cells grouped to store a word, wherein the memory cells are organized into a plurality of ripple groups, each ripple group including a complex logic gate configured to determine whether a stored content for the ripple group's memory cells matches a corresponding portion of a comparand word if an enable input for the ripple group is asserted, each complex logic gate asserting an output if the determination indicates a match, the ripple groups being arranged from a first ripple group to a last ripple group such that the output from the first ripple group's complex logic gate functions as the enable input for a second ripple group's complex logic gate and so on such that an output from a next-to-last ripple group's complex logic gate functions as the enable input for the last ripple group's complex logic gate.

Abstract: The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a multi-bank memory. The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit adapted to complete a word for a failing bank in the multi-bank memory.

Abstract: The present invention relates to a system and method for equalizing the capacitance between/among n lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the n lines using an algorithm for example. After determining the twisting pattern forming at least n?1 twisted sections, the n lines are twisted according to the pattern so that each of the n lines runs along every other line for a same distance across the length of a bus.

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Abstract: An imaging device includes a plurality of photo-diodes that operate as optical pixels arranged in a plurality of columns on a single CMOS substrate. The outputs of the multiple pixel sensors, or photo-diodes, are examined to determine if a one pixel, or a region of pixels are in saturation. If so, then the pixel gain is adjusted to correct or compensate for the image distortion in the region. For example, the gain of the charging amplifier or operational amplifier can be adjusted to correct for saturation. This can be done in real-time since hardware is being tuned for the correction instead of software.

Abstract: In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one redundant predecoder adapted to be shifted in for at least one active predecoder of a plurality of predecoders adapted to be shifted out.