Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.

Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.

Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a burst packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a burst packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.

Abstract: Disclosed is a system of a dynamic range three-dimensional image, including: an optical detector including a gain control terminal capable of controlling an optical amplification gain; a pixel detecting module for detecting a pixel signal for configuring an image by receiving an output of the optical detector; a high dynamic range (HDR) generating module for acquiring a dynamic range image by generating a signal indicating a saturation degree of the pixel signal and combining the pixel signal based on the pixel signal detected by the pixel detecting module; and a gain control signal generating module generating an output signal for supplying required voltage to the gain control terminal of the optical detector based on the magnitude of the signal indicating the saturation degree of the pixel signal.

Abstract: Provided is an apparatus and method for measuring IQ imbalance, and in particular, is an apparatus and method for measuring IQ imbalance for an optical receiver. The apparatus for measuring IQ imbalance for an optical receiver includes a light generating unit generating optical and reference signals to provide the optical and reference signals to an optical receiver, a graph creating unit creating a Lissajous figure by using an in-phase (I) signal and a quadrature-phase (Q) signal output from the optical receiver in response to the optical and reference signals, and a calculating unit calculating IQ imbalance for the optical receiver with reference to the Lissajous figure.

Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.

Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.

Abstract: Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased.

Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.

Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.

Abstract: Provided is a method of measuring signal transmission time difference of a measuring device. The measuring device according to embodiments, by measuring a skew on two optical paths through signal delays of sufficient sizes for skew measurement on the optical paths, even a skew having a minute size can be measured within a measurable range.

Abstract: Disclosed are a GaN (gallium nitride) compound power semiconductor device and a manufacturing method thereof. The gallium nitride compound power semiconductor device includes: a gallium nitride compound element formed by being grown on a wafer; a contact pad including a source, a drain, and a gate connecting with the gallium nitride compound element; a module substrate to which the nitride gallium compound element is flip-chip bonded; a bonding pad formed on the module substrate; and a bump formed on the bonding pad of the module substrate so that the contact pad and the bonding pad are flip-chip bonded.

Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.

Abstract: Disclosed are an avalanche photodiode with a guard ring structure that relieves edge breakdown by an external voltage which is applied through a metal pad which is attached to the guard ring and a manufacturing method thereof. An avalanche photodiode with a guard ring structure includes a plurality of semiconductor layers laminated on a substrate; an active region partially formed above the semiconductor layers; a guard ring which is formed above the semiconductor layers and disposed so as to be spaced apart from the active region and have a ring shape that encloses the active region; and a connecting unit formed on the semiconductor layers to be electrically connected to the guard ring so as to apply an external voltage to the guard ring region. Therefore, the external voltage is applied to the guard ring of the avalanche diode through the connecting unit to relieve the edge breakdown.

Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.

Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract: An apparatus for measuring performance of a coherent optical receiver includes a beam splitter splitting light into first and second paths, a first optical modulator modulating the first path light, a variable optical attenuator controlling an optical power of the first optical modulator, a first polarization controller transmitting a signal controlling polarization of an output of the variable optical attenuator to the coherent optical receiver, a second optical modulator modulating the second path light, a variable optical delay line delaying time of an output of the second optical modulator, a second polarization controller transmitting a signal controlling polarization of an output of the variable optical delay line to the coherent optical receiver, a network analyzer measuring performance of the coherent optical receiver and controlling the optical modulators, and a controller transmitting a control signal to the optical modulators.