Patents by Inventor Eun-Soo Nam
Eun-Soo Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140363937Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.Type: ApplicationFiled: June 18, 2014Publication date: December 11, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Woo Jin CHANG, Jong-Won LIM, Ho Kyun AHN, Sang Choon KO, Sung Bum BAE, Chull Won JU, Young Rak PARK, Jae Kyoung MUN, Eun Soo NAM
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Patent number: 8901608Abstract: A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer.Type: GrantFiled: June 3, 2013Date of Patent: December 2, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Jong-Won Lim, Hokyun Ahn, Woojin Chang, Dong Min Kang, Seong-Il Kim, Sang-Heung Lee, Hyung Sup Yoon, Chull Won Ju, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8853821Abstract: Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate.Type: GrantFiled: September 14, 2012Date of Patent: October 7, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Seong-il Kim, Sang-Heung Lee, Jong-Won Lim, Hyung Sup Yoon, Jongmin Lee, Byoung-Gue Min, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8841969Abstract: Disclosed is an automatic gain control feedback amplifier that can arbitrarily control a gain even when a difference in input signal is large. The automatic gain control feedback amplifier includes: an amplification circuit unit configured to amplify voltage input from an input terminal and output the amplified voltage to an output terminal; a feedback circuit unit connected between the input terminal and the output terminal and including a feedback resistor unit of which a total resistance value is determined by one or more control signals and a feedback transistor connected to the feedback resistor unit in parallel; and a bias circuit unit configured to supply predetermined bias voltage to the feedback transistor.Type: GrantFiled: November 6, 2012Date of Patent: September 23, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Sang-Heung Lee, Seong-Il Kim, Dong Min Kang, Jong-Won Lim, Hyung Sup Yoon, Chull Won Ju, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8841154Abstract: Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced.Type: GrantFiled: June 12, 2013Date of Patent: September 23, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Hyung Sup Yoon, Byoung-Gue Min, Jong-Won Lim, Ho Kyun Ahn, Jong Min Lee, Seong-il Kim, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140240691Abstract: Disclosed are a laser radar system and a method for acquiring an image of a target, and the laser radar system includes: a beam source to emit the laser beam; a beam deflector disposed between the beam source and the target, and configured to deflect the laser beam emitted from the beam source in a scanning direction of the target as time elapses; and an optical detector configured to detect the laser beam reflected from the target, which is provided a plurality of beam spots having a diameter DRBS; and a receiving optical system disposed between the target and the optical detector and configured to converge the laser beam reflected from the target, and the optical detector includes a detecting area having a diameter DDA that satisfies an equation of ?{square root over (/2)}×PRBS+2×DRBS?DDA?2×Dlens and an equation of (4/?)×?×F_number<DRBS<Dlens.Type: ApplicationFiled: June 12, 2013Publication date: August 28, 2014Inventors: Bongki MHEEN, MyoungSook Oh, Kisoo Kim, Jae-Sik Sim, Yong-Hwan Kwon, Eun Soo Nam
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Publication number: 20140225121Abstract: Provided are an aluminum gallium nitride template and a fabrication method thereof. The fabrication method includes forming an aluminum nitride (AlN) layer on a substrate, forming a first aluminum gallium nitride (AlxGa1-xN) layer on the aluminum nitride (AlN) layer, forming a second aluminum gallium nitride (AlyGa1-yN) layer on the first aluminum gallium nitride (AlxGa1-xN) layer, forming a third aluminum gallium nitride (AlzGa1-zN) layer on the second aluminum gallium nitride (AlyGal-yN) layer, wherein the first aluminum gallium nitride (AlxGa1-xN) layer, the second aluminum gallium nitride (AlyGa1-yN) layer, and the third aluminum gallium nitride (AlzGa1-zN) layer are formed to have crystal defects and a composition ratio of aluminum (where 1>x>y>z>0) that are gradually decreased as heights of the layers are increased.Type: ApplicationFiled: December 30, 2013Publication date: August 14, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Sung-Bum BAE, Sung Bock KIM, Eun Soo NAM
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Publication number: 20140213045Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Sung Bum BAE, Eun Soo NAM, Jae Kyoung MUN, Sung Bock KIM, Hae Cheon KIM, Chull Won JU, Sang Choon KO, Jong-Won LIM, Ho Kyun AHN, Woo Jin CHANG, Young Rak PARK
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Publication number: 20140205280Abstract: Provided is a method of measuring signal transmission time difference of a measuring device. The measuring device according to embodiments, by measuring a skew on two optical paths through signal delays of sufficient sizes for skew measurement on the optical paths, even a skew having a minute size can be measured within a measureable range.Type: ApplicationFiled: July 3, 2013Publication date: July 24, 2014Inventors: Joong-Seon CHOE, Chun Ju YOUN, Jong-Hoi KIM, Duk Jun KIM, Yong-Hwan KWON, Kwang-Seong CHOI, Eun Soo NAM
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Patent number: 8772833Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.Type: GrantFiled: August 23, 2012Date of Patent: July 8, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Woo Jin Chang, Jong Won Lim, Ho Kyun Ahn, Sang Choon Ko, Sung Bum Bae, Chull Won Ju, Young Rak Park, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140184333Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a bust packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a bust packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.Type: ApplicationFiled: July 25, 2013Publication date: July 3, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Sang-Heung LEE, Seong-il Kim, Dong Min Kang, Jong-Won Lim, Chull Won Ju, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140179088Abstract: The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern.Type: ApplicationFiled: May 20, 2013Publication date: June 26, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Sung-Bum BAE, Sung Bock Kim, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 8759204Abstract: The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern.Type: GrantFiled: May 20, 2013Date of Patent: June 24, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Sung-Bum Bae, Sung Bock Kim, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140167806Abstract: Provided is a semiconductor device testing apparatus including a first socket configured to load a package, on which a semiconductor device to be tested may be mounted, and a second socket coupled to the first socket. The first socket may include an upper part including a hole configured to accommodate the package and a terminal pad provided at both side edges of the hole to hold input and output terminals of the package, and a lower part including a heating room, in which a heater and a temperature sensing part may be provided, the heater being configured to heat the semiconductor device and the temperature sensing part being configured to measure temperature of the semiconductor device. The second socket may include a probe card with a pattern that may be configured to receive test signals from an external power source.Type: ApplicationFiled: September 9, 2013Publication date: June 19, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Chul Won JU, Hyung Sup Yoon, Jong-Won Lim, Sang-Heung Lee, Seong-il Kim, Dong Min Kang, Eun Soo Nam, Jae Kyoung Mun
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Publication number: 20140169786Abstract: Provided is an apparatus and method for measuring IQ imbalance, and in particular, is an apparatus and method for measuring IQ imbalance for an optical receiver. The apparatus for measuring IQ imbalance for an optical receiver includes a light generating unit generating optical and reference signals to provide the optical and reference signals to an optical receiver, a graph creating unit creating a Lissajous figure by using an in-phase (I) signal and a quadrature-phase (Q) signal output from the optical receiver in response to the optical and reference signals, and a calculating unit calculating IQ imbalance for the optical receiver with reference to the Lissajous figure.Type: ApplicationFiled: September 16, 2013Publication date: June 19, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Chun Ju YOUN, Jong-Hoi KIM, Joong-Seon CHOE, Duk Jun KIM, Yong-Hwan KWON, Eun Soo NAM
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Publication number: 20140167111Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.Type: ApplicationFiled: June 7, 2013Publication date: June 19, 2014Inventors: Hokyun AHN, Jong-Won Lim, Jeong-Jin Kim, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140167175Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.Type: ApplicationFiled: June 11, 2013Publication date: June 19, 2014Inventors: Seong-Il KIM, Jong-Won Lim, Dong Min Kang, Sang-Heung Lee, Hyung Sup Yoon, Chull Won Ju, Byoung-Gue Min, Jongmin Lee, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140167070Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.Type: ApplicationFiled: July 10, 2013Publication date: June 19, 2014Inventors: Young Rak PARK, Sang Choon Ko, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Sung-Bum Bae, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140160689Abstract: A package includes a ground plate, a chip mounting plate disposed at a side of the ground plate and having a top surface lower than a top surface of the ground plate, a chip on the chip mounting plate, a first input/output terminal opposite to the chip mounting plate and disposed at another side of the ground plate, and a second input/output terminal opposite to the ground plate and disposed at a side of the chip mounting plate. The first and second input/output terminals are electrically connected to the chip.Type: ApplicationFiled: August 5, 2013Publication date: June 12, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Dong Min KANG, Chull Won Ju, Seong-Il Kim, Sang-Heung Lee, Jong-Won Lim, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140159049Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.Type: ApplicationFiled: May 30, 2013Publication date: June 12, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Sang Choon KO, Jae Kyoung Mun, Byoung-Gue Min, Young Rak Park, Hokyun Ahn, Jeong-Jin Kim, Eun Soo Nam