Patents by Inventor Fabrice Letertre

Fabrice Letertre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7071029
    Abstract: Methods for fabricating final substrates for use in optics, electronics, or optoelectronics are described. The method includes forming a zone of weakness beneath a surface of a source substrate to define a transfer layer; detaching the transfer layer from the source substrate along the zone of weakness; depositing a useful layer upon the transfer layer; and depositing a support material on the useful layer to form the final substrate. The useful layer may be deposited on the transfer layer before or after detaching the transfer layer from the source substrate. The useful layer is typically made of a material having a large band gap, and comprises at least one of gallium nitride, or aluminum nitride, or of compounds of at least two elements including at least one element of aluminum, indium, and gallium. The zone of weakness may advantageously be formed by implanting atomic species into the source substrate.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: July 4, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Bruno Ghyselen, Fabrice Letertre
  • Patent number: 7067393
    Abstract: A substrate-assembly having a mechanical stress absorption system. The assembly includes two substrates, one of which has a mechanical stress absorbing system, such as a plurality of motifs that absorb thermoelastic stresses, to prevent cracking or destruction of the substrates or separation of one substrate from the other.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: June 27, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Publication number: 20060125057
    Abstract: The invention relates to an SiCOI type composite substrate manufacturing method comprising the following steps: supply of an initial substrate comprising an Si or SiC support (1) bearing a layer (2) of SiO2 whereon a thin layer (3) of SiC is transferred, epitaxy of SiC (4) on the thin layer (3) of SiC. The epitaxy is conducted at the following temperatures from 1450° C. to obtain 6H or 4H polytype epitaxy (4) on a transferred thin 6H or 4H polytype layer (3) respectively, if the support (1) consists of SiC, from 1350° C. to obtain 3C polytype epitaxy (4) on a transferred thin 3C polytype layer (3), if the support (1) consists of Si or SiC, from 1350° C. to obtain 6H or 4H polytype epitaxy (4) on a transferred thin 6H or 4H polytype layer (3) respectively, if the support (1) consists of Si.
    Type: Application
    Filed: September 1, 2003
    Publication date: June 15, 2006
    Inventors: Lea Di Cioccio, Francois Templier, Thierry Billon, Fabrice Letertre
  • Publication number: 20060110899
    Abstract: Improved fabrication processes for manufacturing GeOI type wafers are disclosed. In an implementation, a method for fabricating a germanium on insulator wafer includes providing a source substrate having a surface, at least a layer of germanium and a weakened area. The weakened area is located at a predetermined depth in the germanium layer of the source substrate and is generally parallel to the source substrate surface. The technique also includes providing a germanium oxynitride layer in or on the source substrate, bonding the source substrate surface to a handle substrate to form a source-handle structure, and detaching the source substrate from the source-handle structure at the weakened area of the source substrate to create the germanium on insulator wafer having, as a surface, a useful layer of germanium.
    Type: Application
    Filed: January 4, 2005
    Publication date: May 25, 2006
    Inventors: Konstantin Bourdelle, Fabrice Letertre, Bruce Faure, Christophe Morales, Chrystel Deguet
  • Patent number: 7041577
    Abstract: A process for producing a substrate is described. The process includes providing an assembly having a first layer weakly bonded to a temporary support at an interface therebetween. At least a portion of the first layer is selectively etched substantially to the interface to create an etched zone. A second layer is then bonded to un-etched portions of the first layer to cover the etched zone and to form a closed cavity. The first layer is detached from the temporary support at the weak bond by providing a raised pressure in the cavity.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: May 9, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Olivier Rayssac, Fabrice Letertre
  • Publication number: 20060076559
    Abstract: A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion.
    Type: Application
    Filed: November 22, 2005
    Publication date: April 13, 2006
    Inventors: Bruce Faure, Fabrice Letertre
  • Publication number: 20060079071
    Abstract: The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps: a) formation of a thin layer starting from an initial substrate, the thin layer having a free face called the first contact face, b) putting the first contact face into bonding contact with a face of an intermediate support, the structure obtained being compatible with later thinning of the initial substrate, c) thinning of the said initial substrate to expose a free face of the thin layer called the second contact face and opposite the first contact face, d) putting a face of the target substrate into bonding contact with at least part of the second contact face, the structure obtained being compatible with later removal of all or some of the intermediate support, e) removal of at least part of the intermediate support in order to obtain the said stacked structure.
    Type: Application
    Filed: September 23, 2005
    Publication date: April 13, 2006
    Inventors: Hubert Moriceau, Bernard Aspar, Eric Jalaguier, Fabrice Letertre
  • Publication number: 20060079070
    Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.
    Type: Application
    Filed: November 28, 2005
    Publication date: April 13, 2006
    Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Publication number: 20060076649
    Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.
    Type: Application
    Filed: November 28, 2005
    Publication date: April 13, 2006
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Patent number: 7022586
    Abstract: The present invention relates to a method for recycling a substrate that has a residue on its surface and a detachment profile resulting from an implantation process. The method includes removing the residue from the substrate to a level substantially equivalent to that of the detachment profile, thus obtaining a substantially uniform planar surface on the substrate, and then polishing the entire surface of the substrate to eliminate defects.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: April 4, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Christophe Maleville, Fabrice Letertre, Thibaut Maurice, Carlos Mazure, Fredéric Metral
  • Publication number: 20060060922
    Abstract: A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implantation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties.
    Type: Application
    Filed: November 16, 2005
    Publication date: March 23, 2006
    Applicants: S.O.I.Tec Silicon on Insulator Technologies S.A., Commissariat a l'Energie Atomique (CEA)
    Inventors: Fabrice Letertre, Yves Le Vaillant, Eric Jalaguier
  • Patent number: 7008859
    Abstract: A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implantation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: March 7, 2006
    Assignees: S.O.I.Tec Silicon on Insulator Technologies S.A., Commissariat à l'Energie Atomique (CEA)
    Inventors: Fabrice Letertre, Yves Mathieu Le Vaillant, Eric Jalaguier
  • Patent number: 7009270
    Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: March 7, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Fabrice Letertre, Bruno Ghyselen, Oliver Rayssac
  • Publication number: 20060035440
    Abstract: A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined between facing surfaces of the nucleation layer and support. A substrate of a relatively thicker layer of a third material is grown, by epitaxy on the nucleation layer, to form a second assembly with the substrate attaining a sufficient thickness to be free-standing. The third material is preferably a monocrystalline material. Also, the removable character of the bonding interface is preserved with at least the substrate being heated to an epitaxial growth temperature.
    Type: Application
    Filed: August 29, 2005
    Publication date: February 16, 2006
    Inventors: Bruno Ghyselen, Fabrice Letertre, Carlos Mazure
  • Publication number: 20050282358
    Abstract: A method for transferring an electrically active thin film from an initial substrate to a target substrate including: ion implantation through one face of the initial substrate to create a buried, embrittled film at a determined depth relative to the implanted face of the initial substrate, thus delimiting a thin film between the implanted face and the buried face; fastening the implanted face of the initial substrate with a face of the target substrate; separating the thin film from the remainder of the initial substrate at the level of the buried film; and thinning down the thin film transferred on the target substrate. The implantation dosage, energy, and current are chosen, during the ion implantation, so that concentration in implantation defects is less than a determined threshold, resulting in, within the thinned down thin film, a number of acceptor defects compatible with desired electrical properties of the thin film.
    Type: Application
    Filed: July 15, 2003
    Publication date: December 22, 2005
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE, S.O.I TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Lea Di Cioccio, Fabrice Letertre, Elsa Hugonnard-Bruyere
  • Patent number: 6974759
    Abstract: The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps: a) formation of a thin layer starting from an initial substrate, the thin layer having a free face called the first contact face, b) putting the first contact face into bonding contact with a face of an intermediate support, the structure obtained being compatible with later thinning of the initial substrate, c) thinning of the said initial substrate to expose a free face of the thin layer called the second contact face and opposite the first contact face, d) puffing a face of the target substrate into bonding contact with at least part of the second contact face, the structure obtained being compatible with later removal of all or some of the intermediate support, e) removal of at least part of the intermediate support in order to obtain the said stacked structure.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: December 13, 2005
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Bernard Aspar, Eric Jalaguier, Fabrice Letertre
  • Patent number: 6974760
    Abstract: Methods for transferring a useful layer of silicon carbide to a receiving substrate are described. In an embodiment, the technique includes implanting at least H+ ions through a front face of a source substrate of silicon carbide with an implantation energy E greater than or equal to 95 keV and an implantation dose D chosen to form an optimal weakened zone near a mean implantation depth, the optimal weakened zone defining the useful layer and a remainder portion of the source substrate. The method also includes bonding the front face of the source substrate to a contact face of the receiving substrate, and detaching the useful layer from the remainder portion of the source substrate along the weakened zone while minimizing or avoiding forming an excess zone of silicon carbide material at the periphery of the useful layer that was not transferred to the receiving substrate during detachment. Such a method facilitates recycling the remainder portion of the source substrate.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: December 13, 2005
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Bruno Ghyselen, Fabrice Letertre
  • Publication number: 20050266626
    Abstract: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method.
    Type: Application
    Filed: June 24, 2005
    Publication date: December 1, 2005
    Inventors: Bruce Faure, Fabrice Letertre, Bruno Ghyselen
  • Publication number: 20050266659
    Abstract: Methods for transferring a useful layer of silicon carbide to a receiving substrate are described. In an embodiment, the invention relates to a method for recycling of a silicon carbide source substrate by removal of the excess zone followed by a finishing step to prepare the source substrate for recycling and reuse. Preferably, the excess zone is removed by a thermal budget where the temperature and time of such treatment causes exfoliation of the excess zone. The finishing step is performed in a manner to provide the desired surface roughness for the substrate so that it can be recycled for re-use. The technique includes implanting at least H+ ions through a front face of a source substrate of silicon carbide with an implantation energy E greater than or equal to 95 keV and an implantation dose D chosen to form an optimal weakened zone near a mean implantation depth, the optimal weakened zone defining the useful layer and a remainder portion of the source substrate.
    Type: Application
    Filed: August 4, 2005
    Publication date: December 1, 2005
    Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Bruno Ghyselen, Fabrice Letertre
  • Publication number: 20050258483
    Abstract: The invention relates to a power semiconducting device made from a semiconducting material epitaxied on a stacked structure (10) comprising a layer of semiconducting material (13) transferred onto a first face of a support substrate (11) and fixed to the support substrate by an electrically insulating layer (12), the support substrate comprising electrically conducting means between said first face and a second face, the transferred layer of semiconducting material (13) acting as an epitaxy support for the epitaxied semiconducting material (14, 15).
    Type: Application
    Filed: September 1, 2003
    Publication date: November 24, 2005
    Applicant: Commissariat a l'ENERGIE ATOMIQUE
    Inventors: Francois Templier, Lea Di Cioccio, Thierry Billon, Fabrice Letertre