Abstract: A memory device includes a polycrystalline germanium-containing semiconductor source line layer containing germanium at an atomic percentage greater than 50%, an alternating stack of insulating layers and electrically conductive layers located over the polycrystalline germanium-containing semiconductor source line layer, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel having an end surface in electrical contact with the polycrystalline germanium-containing semiconductor source line layer, and an interfacial metal alloy layer located between the polycrystalline germanium-containing semiconductor source line layer and a bottommost insulating layer within the alternating stack.

Abstract: A device structure includes a layer stack that includes a first alternating stack of first insulating layers and first electrically conductive layers which overlies a base material layer, and an opening fill structure vertically extending through each layer within the layer stack and laterally enclosed by or contacted by the first alternating stack. The opening fill structure includes a first portion having a first variable width that increases linearly with a vertical distance from the base material layer, a second portion that overlies and is adjoined to the first portion and having a second variable width that decreases non-linearly with the vertical distance from the base material layer and laterally bounded by a tapered annular surface segment having a convex vertical profile, and a third portion that overlies the second portion and having a third variable width that increases linearly with the vertical distance from the base material layer.

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a first backside trench fill structure and a second backside trench fill structure. Each of the electrically conductive layers includes a respective metal nitride liner and a respective metal fill material region. The respective metal fill material region includes a respective first-thickness portion having a respective first vertical thickness and a respective second-thickness portion having a respective second vertical thickness that is greater than the respective first vertical thickness.

Abstract: A semiconductor structure includes a base substrate including a first region and a second region. The semiconductor further includes a first fin member located over the first region, a second fin member located over the second region, a first dummy gate across a surface of the first fin member, and a second dummy gate across a surface of the second fin member. A first opening is formed in the first fin member located on each side of the first dummy gate, a second opening is formed between two adjacent first channel layers, a third opening is formed in the second fin member located at each side of the second dummy gate, and a fourth opening is formed between two second channel layers. The semiconductor structure still further includes a first inner spacer located in the second opening, and a second inner spacer located in the fourth opening.

Abstract: A miter saw has a base having a detent notch, a table rotatably connectable to the base, a pivoting assembly connected to the table, and a saw assembly supported by the pivoting assembly. The saw assembly has a blade movable downwardly for a cutting operation. A locking mechanism is disposed on the table. The locking mechanism is movable between an unlocked position and a locked position for selectively unlocking and locking the table for rotational movement relative to the base about the miter axis. The locking mechanism has a lock lever rotatably connected to the table. The lock lever has a handle for moving locking mechanism between the locked and unlocked positions. The saw also has a miter detent assembly for selectively engaging and disengaging the detent notch.

Abstract: A semiconductor structure includes a doped single crystalline semiconductor material layer, a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer, a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer, an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer, a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer, a memory film and a vertical semiconductor channel located within the memory opening, such that the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer, and a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material l

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding portions of the memory opening. Each of the ferroelectric memory structures includes crystalline ferroelectric material portion and a crystalline template material portion located between a respective electrically conductive layer of the electrically conductive layers and the crystalline ferroelectric material portion.

Abstract: A three-dimensional memory device includes: a pair of alternating stacks of insulating layers and electrically conductive layers, the pair of alternating stacks being laterally spaced from each other by a lateral isolation trench that generally extends along a first horizontal direction; memory openings vertically extending through a respective one of the pair of alternating stacks; memory opening fill structures located in a respective one of the memory openings; and a lateral isolation trench fill structure including a peripheral spacer and a conductive fill structure, wherein a first vertical cross-sectional view of the lateral isolation trench fill structure in a first vertical plane includes: an outer periphery of the peripheral spacer which includes a horizontal top surface segment located in a first horizontal plane; and an inner periphery of the peripheral spacer that is vertically spaced from, and located entirely below, the first horizontal plane.

Abstract: A semiconductor structure includes a substrate and a vertical stack structure over the substrate. The vertical stack structure includes a channel region and a source/drain region on two sides of the channel region. The channel region includes a first stack region, an isolation region, and a second stack region. The structure also includes a first doped source/drain region, a first contact layer located on a surface of the first doped source/drain region, a second doped source/drain region located over the first contact layer, and a second contact layer located on a surface of the second doped source/drain region. The structure also includes a second connection layer electrically connected to the second doped source/drain region through the second contact layer, and a first connection layer electrically connected to the first doped source/drain region through the first contact layer.

Abstract: Disclosed in the present disclosure is a blockchain network security communication method based on a quantum key. On the basis of a blockchain network formed by means of combining quantum key distribution technology and blockchain technology, the method implements the process of quantum key distribution, acquisition and encryption transmission with simple steps which are easy to control and implement, to ensure the secure conduction of communication services in the blockchain network.

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

Abstract: A memory device includes a semiconductor source line layer containing silicon and electrical dopants, an alternating stack of insulating layers and electrically conductive layers located over the semiconductor source line layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film, a vertical semiconductor channel including silicon that is laterally surrounded by the memory film, and a silicon-germanium structure contacting an end portion of the vertical semiconductor channel and contacting the semiconductor source line.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a memory film, a vertical semiconductor channel, and an aluminum nitride layer that laterally surrounds the memory film.

Abstract: Disclosed are a quantum key-based blockchain network and a data secure transmission method. According to the specific architecture of the blockchain network, a corresponding quantum key distribution network is deployed to provide required quantum keys for blockchain nodes, so as to allow quantum key-based data secure transmission. Therefore, a symmetric key can be provided for blockchain nodes by means of high-security quantum key distribution technology, thereby ensuring that the key cannot be effectively intercepted in a distribution process, and in addition, an unpredictable true random number is generated by means of a quantum random number source, thereby ensuring that it is difficult to predict the random number and thus greatly improving the security of the symmetric key and improving the security of data transmission between blockchain nodes.

Abstract: A semiconductor structure and a method for forming the same are provided. One form of a semiconductor structure includes: a substrate including a device unit region, where the device unit region includes a first sub-unit region configured to form a first device and a second sub-unit region configured to form a second device, where a driving current of the first device is greater than a driving current of the second device; a fin protruding from the substrate; a first gate spanning the fin in the first sub-unit region; and a second gate spanning the fin in the second sub-unit region. In some implementations, the second sub-unit region is disposed in the device unit region, and the second device generates less heat than the first device. Therefore, compared with a solution in which the device unit region includes only a first device region, overall heat from the device unit region can be reduced, thus ameliorating a self-heating effect in the device unit region and enhancing the performance of semiconductors.

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

Abstract: In a method and an apparatus for controlling heating of a vehicle battery, the method includes: obtaining, by a receiver, an ambient temperature of a vehicle and battery output power; determining, by a controller, whether the ambient temperature is lower than a predetermined ambient temperature threshold; when it is determined that the ambient temperature is lower than the predetermined ambient temperature threshold, determining, by the controller, whether a battery heating setting is on; and when it is determined that the battery heating setting is on, controlling, by the controller, the heating of the vehicle battery so that the battery output power is between a first reference power and a second reference power.

Abstract: Disclosed in the present disclosure is a blockchain network security communication method based on a quantum key. On the basis of a blockchain network formed by means of combining quantum key distribution technology and blockchain technology, the method implements the process of quantum key distribution, acquisition and encryption transmission with simple steps which are easy to control and implement, to ensure the secure conduction of communication services in the blockchain network.