Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a memory film, a vertical semiconductor channel, and an aluminum nitride layer that laterally surrounds the memory film.

Abstract: Disclosed are a quantum key-based blockchain network and a data secure transmission method. According to the specific architecture of the blockchain network, a corresponding quantum key distribution network is deployed to provide required quantum keys for blockchain nodes, so as to allow quantum key-based data secure transmission. Therefore, a symmetric key can be provided for blockchain nodes by means of high-security quantum key distribution technology, thereby ensuring that the key cannot be effectively intercepted in a distribution process, and in addition, an unpredictable true random number is generated by means of a quantum random number source, thereby ensuring that it is difficult to predict the random number and thus greatly improving the security of the symmetric key and improving the security of data transmission between blockchain nodes.

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

Abstract: A semiconductor structure and a method for forming the same are provided. One form of a semiconductor structure includes: a substrate including a device unit region, where the device unit region includes a first sub-unit region configured to form a first device and a second sub-unit region configured to form a second device, where a driving current of the first device is greater than a driving current of the second device; a fin protruding from the substrate; a first gate spanning the fin in the first sub-unit region; and a second gate spanning the fin in the second sub-unit region. In some implementations, the second sub-unit region is disposed in the device unit region, and the second device generates less heat than the first device. Therefore, compared with a solution in which the device unit region includes only a first device region, overall heat from the device unit region can be reduced, thus ameliorating a self-heating effect in the device unit region and enhancing the performance of semiconductors.

Abstract: In a method and an apparatus for controlling heating of a vehicle battery, the method includes: obtaining, by a receiver, an ambient temperature of a vehicle and battery output power; determining, by a controller, whether the ambient temperature is lower than a predetermined ambient temperature threshold; when it is determined that the ambient temperature is lower than the predetermined ambient temperature threshold, determining, by the controller, whether a battery heating setting is on; and when it is determined that the battery heating setting is on, controlling, by the controller, the heating of the vehicle battery so that the battery output power is between a first reference power and a second reference power.

Abstract: Disclosed in the present disclosure is a blockchain network security communication method based on a quantum key. On the basis of a blockchain network formed by means of combining quantum key distribution technology and blockchain technology, the method implements the process of quantum key distribution, acquisition and encryption transmission with simple steps which are easy to control and implement, to ensure the secure conduction of communication services in the blockchain network.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, etch stop plates located in the staircase region, laterally and vertically spaced apart among one another, and overlying an end portion of a respective one of the electrically conductive layers, and contact via structures located in a staircase region, vertically extending through a respective one of the etch stop plates, and contacting a respective one of the electrically conductive layers.

Abstract: Semiconductor structures and fabrication methods are provided. The semiconductor includes a substrate; a plurality of discrete fins on the substrate; a gate structure on the substrate, and across the plurality of discrete fins by covering portions of sidewall surfaces and top surfaces of the plurality of discrete fins; a plurality of doped source/drain layers in the plurality of discrete fins and at both sides of the gate structure; a conductive layer, formed at one or two sides of the gate structure, connecting multiple doped source/drain layers of the plurality of doped source/drain layers, and with a top surface lower than a top surface of the gate structure; and a conductive plug on the conductive layer and in contact with a portion of a surface of the conductive layer.

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, where a smallest unit shape of three nearest neighbor memory openings is a non-equilateral triangle, and memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements.

Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers including a first insulating material and sacrificial material layers including a first sacrificial material over a substrate, forming a memory opening through the alternating stack, performing a first selective material deposition process that selectively grows a second sacrificial material from physically exposed surfaces of the sacrificial material layers to form a vertical stack of sacrificial material portions; forming a memory opening fill structure in the memory opening, where the memory opening fill structure includes a vertical stack of memory elements and a vertical semiconductor channel, and replacing a combination of the vertical stack of sacrificial material portions and the sacrificial material layers with electrically conductive layers.

Abstract: A miter saw has a base having a detent notch, a table rotatably connectable to the base, a pivoting assembly connected to the table, and a saw assembly supported by the pivoting assembly. The saw assembly has a blade movable downwardly for a cutting operation. A locking mechanism is disposed on the table. The locking mechanism is movable between an unlocked position and a locked position for selectively unlocking and locking the table for rotational movement relative to the base about the miter axis. The locking mechanism has a lock lever rotatably connected to the table. The lock lever has a handle for moving locking mechanism between the locked and unlocked positions. The saw also has a miter detent assembly for selectively engaging and disengaging the detent notch.

Abstract: Embodiments of this application provide a method for running a boot program of an electronic device, and an electronic device. In the method, the boot program in embodiments of this application may include two BIOSs, where one is a primary BIOS, and the other is a secondary BIOS. The electronic device stores the entire primary BIOS in a first storage, and stores some program blocks in the secondary BIOS in a second storage. When the primary BIOS is damaged, the electronic device may determine storage locations of program blocks in the secondary BIOS in the second storage, load these program blocks into a memory of the electronic device, and then run the program blocks in the secondary BIOS, so that the electronic device is powered on normally.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer, a continuous charge storage material layer vertically extending through a plurality of the electrically conductive layers, a vertical stack of discrete charge storage elements located at levels of the electrically conductive layers and contacting a respective surface segment of an outer sidewall of the continuous charge storage material layer, and a vertical stack of discrete blocking dielectric material portions containing silicon atoms and oxygen atoms and located at the levels of the electrically conductive layers and vertically spaced apart from each other.

Abstract: A semiconductor structure and a method for forming the same are provided. One form of a method for forming a semiconductor structure includes: providing a base, the base including a first device region and a second device region, the base including an initial substrate and one or more initial channel stacks located on the initial substrate, and the initial channel stack including a sacrificial material layer and a channel material layer located on the sacrificial material layer; forming a discrete combined pattern on the initial channel stack, the combined pattern including a mandrel layer and a spacer layer located on a side wall of the mandrel layer, and the combined pattern exposing a boundary between the first device region and the second device region; forming a dielectric wall running through the initial channel stack at the boundary between the first device region and the second device region; and removing the mandrel layer.

Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

Abstract: A mode setting method and a mode setting device for a monitoring system are provided. The mode setting method includes: selecting one or a plurality of monitoring objects; selecting a corresponding display template from preset display templates for each of the one or the plurality of monitoring objects, and associating and packaging each of the one or the plurality of monitoring objects and the selected display template in a one-to-one correspondence, and generating one or a plurality of single display units; selecting a single display unit from the generated single display units according to a monitoring scene; and placing the selected single display unit into a corresponding block of a monitoring interface layout of the monitoring system, and storing the same.