Patents by Inventor Fei Zhou

Fei Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220004315
    Abstract: A method includes displaying N candidate devices, receiving a first selection operation that a user selects a second electronic device from the N candidate devices, and switch multimedia data associated with the first display interface to the second electronic device for playing or displaying the task.
    Type: Application
    Filed: October 15, 2019
    Publication date: January 6, 2022
    Inventors: Yanan Zhang, Xuan Zhou, Mengdi Liu, Fei Ye, Guyu Xie
  • Publication number: 20220000327
    Abstract: A cleaning robot and an automatic cleaning method thereof, to implement automatic cleaning. The cleaning robot includes a lifting mechanism and a cleaning base, where the cleaning base includes a base body, a scraping mechanism disposed on the base body, and a spraying assembly provided with nozzles. The nozzles are arranged along a mopping component of the cleaning robot and formed into a structure for spraying water or mist to the mopping component. The scraping mechanism includes a scraper, and the scraper comes into contact with and moves relative to the mopping component, to scrape off the attachment on the mopping component while squeezing out the water. The lifting mechanism causes the mopping component to lift or move down by causing the mopping component to come into contact with or separate from the scraper.
    Type: Application
    Filed: November 19, 2019
    Publication date: January 6, 2022
    Inventors: Kejia ZHANG, Sihai ZHOU, Fei LIU, Wei LI
  • Patent number: 11215909
    Abstract: A light source system includes a first light source emitting first laser; a wavelength conversion device; a driver device driving the wavelength conversion device to move in such a manner that regions of the wavelength conversion device sequentially and periodically receive the first laser; a second light source emitting supplementary light consistent in color with light emitted by one primary color light region; a control device controlling on and off of the second light source, the control device controlling the second light source to be on in at least two of: every time period during which a primary color light region of a same color is receiving the first laser, every time period during which the mixed color light region is receiving the first laser, and some time periods during which a primary color light region of a different color is receiving the first laser.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: January 4, 2022
    Assignee: APPOTRONICS CORPORATION LIMITED
    Inventors: Fei Hu, Yuxuan Zhou, Yi Li
  • Patent number: 11217532
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 4, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar, Tatsuya Hinoue, Tomoyuki Obu, Tomohiro Uno, Yusuke Mukae
  • Publication number: 20210408031
    Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall of each vertical semiconductor channel in the memory opening fill structures. A metal-containing layer is deposited on physically exposed surfaces of the vertical semiconductor channel and the vertical semiconductor channel is crystallized using metal-induced lateral crystallization. Alternatively or additionally, cylindrical metal-semiconductor alloy regions can be formed around the vertical semiconductor channels to reduce contact resistance. A source contact layer can be formed in the source cavity.
    Type: Application
    Filed: June 24, 2020
    Publication date: December 30, 2021
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Adarsh RAJASHEKHAR
  • Publication number: 20210408280
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are disclosed. One form a semiconductor structure includes: a substrate, comprising a first region used to form a well region and a second region used to form a drift region, wherein the first region is adjacent to the second region; and a fin, protruding out of the substrate, wherein the fins comprise first fins located at a junction of the first region and the second region and second fins located on the second region, and a quantity of the second fins is greater than a quantity of the first fins.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Fei ZHOU
  • Publication number: 20210398901
    Abstract: Semiconductor structures and fabrication methods are provided. The semiconductor includes a substrate; a plurality of discrete fins on the substrate; a gate structure on the substrate, and across the plurality of discrete fins by covering portions of sidewall surfaces and top surfaces of the plurality of discrete fins; a plurality of doped source/drain layers in the plurality of discrete fins and at both sides of the gate structure; a conductive layer, formed at one or two sides of the gate structure, connecting multiple doped source/drain layers of the plurality of doped source/drain layers, and with a top surface lower than a top surface of the gate structure; and a conductive plug on the conductive layer and in contact with a portion of a surface of the conductive layer.
    Type: Application
    Filed: May 21, 2021
    Publication date: December 23, 2021
    Inventor: Fei ZHOU
  • Publication number: 20210397170
    Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Fei Zhou, Cheng-Chung Chu, Raghuveer Makala
  • Publication number: 20210395784
    Abstract: The application belongs to the field of nucleic acid editing, in particular to the field of clustered regularly interspaced short palindromic repeats (CRISPR) technology. In particular, the application provides a Cas effector protein, a fusion protein with the Cas effector protein, and a nucleic acid molecule encoding the same. Also provided are a compound and a composition for nucleic acid editing (e.g., gene or genome editing) with the protein or the nucleic acid molecule, and a method for nucleic acid editing (e.g., gene or genome editing) using the protein.
    Type: Application
    Filed: October 29, 2019
    Publication date: December 23, 2021
    Inventors: Jinsheng LAI, Yingsi ZHOU, Jinjie ZHU, Fei YI, Xiangbo ZHANG, Haiming ZHAO, Weibin SONG
  • Publication number: 20210397637
    Abstract: An information processing device, an information processing method, a computer readable storage medium are provided. The information processing device comprises processing circuitry configured to: construct, for each of a plurality of indexes, a sample unit set for the index based on a plurality of minimum labeled sample units related to the index which are obtained and labeled from an original sample set; and extract, for at least a part of the constructed plurality of sample unit sets, a minimum labeled sample unit from each sample unit set, and generate a labeled training sample based on the extracted minimum labeled sample unit. A sample unit set is constructed based on minimum labeled sample units that are labeled manually, and a labeled training sample is generated automatically based on such sample unit sets, thereby generating the labeled training sample automatically to a certain degree, and reducing manual participation.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 23, 2021
    Applicant: Sony Group Corporation
    Inventors: Shuangfei ZHOU, Fei CAO
  • Patent number: 11203830
    Abstract: A delivery device includes: a detergent container having a flow space and a withdrawal space, the flow space having a first inlet, a second inlet, a water inlet and a liquid outlet; a dispenser provided in the withdrawal space and capable of being pushed into and pulled out of the withdrawal space, the dispenser having two placing cavities spaced apart from each other, and each placing cavity having a delivery opening and a liquid discharge channel; and a pump having two inflow openings and two outflow openings. The two inflow openings are connected with the two liquid discharge channels respectively. The two outflow openings are connected with the first inlet and the second inlet respectively.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: December 21, 2021
    Assignee: WUXI LITTLE SWAN ELECTRIC CO., LTD.
    Inventors: Haifeng Wang, Chanwi Park, Fei Peng, Wei Zhou, Yihua Zhou, Lei Fan, Haixu Jiang
  • Patent number: 11205721
    Abstract: A semiconductor device and its fabrication method are provided. The method includes providing a base substrate; forming a first well region and a second well region in the base substrate; forming a gate electrode structure, sidewall spacers, a doped source layer, a doped drain layer and a dielectric layer over the base substrate, where the doped source layer and the doped drain layer are respectively on two sides of the gate electrode structure and the sidewall spacers, and the gate electrode structure and the sidewall spacers are over the first well region and the second well region; removing a portion of the gate electrode structure on the second well region and a portion of the base substrate of the second well region to form a trench in the dielectric layer, where the trench exposes a portion of the sidewall spacers; and forming an isolation layer in the trench.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 21, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11201139
    Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: December 14, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Senaka Kanakamedala, Fei Zhou
  • Publication number: 20210375848
    Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Inventors: Fei ZHOU, Raghuveer S. MAKALA, Rahul SHARANGPANI, Adarsh RAJASHEKHAR
  • Patent number: 11189711
    Abstract: A semiconductor device includes a semiconductor substrate; a plurality of semiconductor fin structures formed on the semiconductor substrate; a plurality of gate structures, each formed on a semiconductor fin structure; a source electrode and a drain electrode formed on two opposite sides of each gate structure, wherein, at least a portion of the source electrode and at least a portion of the drain electrode are formed in the semiconductor fin structure; a covering layer formed on the semiconductor fin structures and also on two side surfaces of each gate structure; and an interlayer dielectric layer formed on the covering layer, wherein the interlayer dielectric layer covers each source electrode and each drain electrode, a trench is formed in the interlayer dielectric layer to expose a portion of each semiconductor fin structure, and a gate structure is formed in each trench.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: November 30, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Publication number: 20210358952
    Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Raghuveer S. Makala, Yanli ZHANG, Fei ZHOU, Rahul SHARANGPANI, Adarsh RAJASHEKHAR, Seung-Yeul YANG
  • Publication number: 20210360340
    Abstract: A speaker comprises a housing having an opening; a waterproof sound-transmission membrane disposed on the housing to cover the opening of the housing; a speaker unit housed in the housing, the speaker unit comprising a speaker having a diaphragm; and an annular polymer membrane disposed between the diaphragm and the waterproof sound-transmission membrane, the annular polymer membrane comprising a through-opening in a radial direction with respect to the annular polymer membrane.
    Type: Application
    Filed: January 17, 2018
    Publication date: November 18, 2021
    Inventor: Peng-Fei Zhou
  • Publication number: 20210358931
    Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Raghuveer S. MAKALA, Yanli ZHANG, Fei ZHOU, Rahul SHARANGPANI, Adarsh RAJASHEKHAR, Seung-Yeul YANG
  • Publication number: 20210358942
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Adarsh RAJASHEKHAR, Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Yanli ZHANG
  • Patent number: 11177280
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Yanli Zhang