Patents by Inventor Fei Zhou

Fei Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12289889
    Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding portions of the memory opening. Each of the ferroelectric memory structures includes crystalline ferroelectric material portion and a crystalline template material portion located between a respective electrically conductive layer of the electrically conductive layers and the crystalline ferroelectric material portion.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: April 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Kartik Sondhi, Adarsh Rajashekhar, Fei Zhou, Raghuveer S. Makala
  • Publication number: 20250107079
    Abstract: A three-dimensional memory device includes: a pair of alternating stacks of insulating layers and electrically conductive layers, the pair of alternating stacks being laterally spaced from each other by a lateral isolation trench that generally extends along a first horizontal direction; memory openings vertically extending through a respective one of the pair of alternating stacks; memory opening fill structures located in a respective one of the memory openings; and a lateral isolation trench fill structure including a peripheral spacer and a conductive fill structure, wherein a first vertical cross-sectional view of the lateral isolation trench fill structure in a first vertical plane includes: an outer periphery of the peripheral spacer which includes a horizontal top surface segment located in a first horizontal plane; and an inner periphery of the peripheral spacer that is vertically spaced from, and located entirely below, the first horizontal plane.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Inventors: Fei ZHOU, Fumitaka AMANO, Rahul SHARANGPANI, Senaka KANAKAMEDALA
  • Publication number: 20250048728
    Abstract: A semiconductor structure includes a substrate and a vertical stack structure over the substrate. The vertical stack structure includes a channel region and a source/drain region on two sides of the channel region. The channel region includes a first stack region, an isolation region, and a second stack region. The structure also includes a first doped source/drain region, a first contact layer located on a surface of the first doped source/drain region, a second doped source/drain region located over the first contact layer, and a second contact layer located on a surface of the second doped source/drain region. The structure also includes a second connection layer electrically connected to the second doped source/drain region through the second contact layer, and a first connection layer electrically connected to the first doped source/drain region through the first contact layer.
    Type: Application
    Filed: December 24, 2021
    Publication date: February 6, 2025
    Inventor: Fei ZHOU
  • Patent number: 12217965
    Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: February 4, 2025
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Rahul Sharangpani, Raghuveer S. Makala, Yujin Terasawa, Naoki Takeguchi, Kensuke Yamaguchi, Masaaki Higashitani
  • Patent number: 12219052
    Abstract: Disclosed in the present disclosure is a blockchain network security communication method based on a quantum key. On the basis of a blockchain network formed by means of combining quantum key distribution technology and blockchain technology, the method implements the process of quantum key distribution, acquisition and encryption transmission with simple steps which are easy to control and implement, to ensure the secure conduction of communication services in the blockchain network.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: February 4, 2025
    Assignee: JINAN INSTITUTE OF QUANTUM TECHNOLOGY
    Inventors: Fei Zhou, Jie Gao
  • Publication number: 20250040139
    Abstract: A memory device includes a semiconductor source line layer containing silicon and electrical dopants, an alternating stack of insulating layers and electrically conductive layers located over the semiconductor source line layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film, a vertical semiconductor channel including silicon that is laterally surrounded by the memory film, and a silicon-germanium structure contacting an end portion of the vertical semiconductor channel and contacting the semiconductor source line.
    Type: Application
    Filed: August 5, 2024
    Publication date: January 30, 2025
    Inventors: Fei ZHOU, Kartik SONDHI, Senaka KANAKAMEDALA, Wei CAO
  • Publication number: 20250008730
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a memory film, a vertical semiconductor channel, and an aluminum nitride layer that laterally surrounds the memory film.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU
  • Publication number: 20240430080
    Abstract: Disclosed are a quantum key-based blockchain network and a data secure transmission method. According to the specific architecture of the blockchain network, a corresponding quantum key distribution network is deployed to provide required quantum keys for blockchain nodes, so as to allow quantum key-based data secure transmission. Therefore, a symmetric key can be provided for blockchain nodes by means of high-security quantum key distribution technology, thereby ensuring that the key cannot be effectively intercepted in a distribution process, and in addition, an unpredictable true random number is generated by means of a quantum random number source, thereby ensuring that it is difficult to predict the random number and thus greatly improving the security of the symmetric key and improving the security of data transmission between blockchain nodes.
    Type: Application
    Filed: May 25, 2022
    Publication date: December 26, 2024
    Inventors: Fei ZHOU, Jie GAO
  • Patent number: 12176203
    Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: December 24, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Rahul Sharangpani, Raghuveer S. Makala, Yujin Terasawa, Naoki Takeguchi, Kensuke Yamaguchi, Masaaki Higashitani
  • Patent number: 12176420
    Abstract: A semiconductor structure and a method for forming the same are provided. One form of a semiconductor structure includes: a substrate including a device unit region, where the device unit region includes a first sub-unit region configured to form a first device and a second sub-unit region configured to form a second device, where a driving current of the first device is greater than a driving current of the second device; a fin protruding from the substrate; a first gate spanning the fin in the first sub-unit region; and a second gate spanning the fin in the second sub-unit region. In some implementations, the second sub-unit region is disposed in the device unit region, and the second device generates less heat than the first device. Therefore, compared with a solution in which the device unit region includes only a first device region, overall heat from the device unit region can be reduced, thus ameliorating a self-heating effect in the device unit region and enhancing the performance of semiconductors.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: December 24, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Publication number: 20240421986
    Abstract: Disclosed in the present disclosure is a blockchain network security communication method based on a quantum key. On the basis of a blockchain network formed by means of combining quantum key distribution technology and blockchain technology, the method implements the process of quantum key distribution, acquisition and encryption transmission with simple steps which are easy to control and implement, to ensure the secure conduction of communication services in the blockchain network.
    Type: Application
    Filed: May 25, 2022
    Publication date: December 19, 2024
    Inventors: Fei ZHOU, Jie GAO
  • Publication number: 20240416798
    Abstract: In a method and an apparatus for controlling heating of a vehicle battery, the method includes: obtaining, by a receiver, an ambient temperature of a vehicle and battery output power; determining, by a controller, whether the ambient temperature is lower than a predetermined ambient temperature threshold; when it is determined that the ambient temperature is lower than the predetermined ambient temperature threshold, determining, by the controller, whether a battery heating setting is on; and when it is determined that the battery heating setting is on, controlling, by the controller, the heating of the vehicle battery so that the battery output power is between a first reference power and a second reference power.
    Type: Application
    Filed: January 9, 2024
    Publication date: December 19, 2024
    Applicants: HYUNDAI MOTOR COMPANY, Kia Corporation
    Inventors: Jian Xiong ZHAO, Fei ZHOU, Won Young JEONG, Cai WU
  • Patent number: 12166125
    Abstract: A semiconductor structure and a method for forming the same are provided.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: December 10, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 12137565
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: November 5, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar
  • Patent number: 12137554
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, etch stop plates located in the staircase region, laterally and vertically spaced apart among one another, and overlying an end portion of a respective one of the electrically conductive layers, and contact via structures located in a staircase region, vertically extending through a respective one of the etch stop plates, and contacting a respective one of the electrically conductive layers.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: November 5, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou
  • Patent number: 12131990
    Abstract: Semiconductor structures and fabrication methods are provided. The semiconductor includes a substrate; a plurality of discrete fins on the substrate; a gate structure on the substrate, and across the plurality of discrete fins by covering portions of sidewall surfaces and top surfaces of the plurality of discrete fins; a plurality of doped source/drain layers in the plurality of discrete fins and at both sides of the gate structure; a conductive layer, formed at one or two sides of the gate structure, connecting multiple doped source/drain layers of the plurality of doped source/drain layers, and with a top surface lower than a top surface of the gate structure; and a conductive plug on the conductive layer and in contact with a portion of a surface of the conductive layer.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: October 29, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 12124247
    Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 22, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Fei Zhou, Cheng-Chung Chu, Raghuveer Makala
  • Publication number: 20240332177
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, where a smallest unit shape of three nearest neighbor memory openings is a non-equilateral triangle, and memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements.
    Type: Application
    Filed: July 31, 2023
    Publication date: October 3, 2024
    Inventors: Ryo NAKAMURA, Fei ZHOU, Rahul SHARANGPANI, Adarsh RAJASHEKHAR, Raghuveer S. MAKALA
  • Patent number: 12096636
    Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: September 17, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Rahul Sharangpani, Fei Zhou
  • Publication number: 20240237346
    Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers including a first insulating material and sacrificial material layers including a first sacrificial material over a substrate, forming a memory opening through the alternating stack, performing a first selective material deposition process that selectively grows a second sacrificial material from physically exposed surfaces of the sacrificial material layers to form a vertical stack of sacrificial material portions; forming a memory opening fill structure in the memory opening, where the memory opening fill structure includes a vertical stack of memory elements and a vertical semiconductor channel, and replacing a combination of the vertical stack of sacrificial material portions and the sacrificial material layers with electrically conductive layers.
    Type: Application
    Filed: July 20, 2023
    Publication date: July 11, 2024
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Adarsh RAJASHEKHAR, Fei ZHOU, Bing ZHOU, Senaka KANAKAMEDALA, Roshan Jayakhar TIRUKKONDA, Kartik SONDHI