Patents by Inventor Fei Zhou

Fei Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11527500
    Abstract: A bonded assembly includes a first semiconductor die that includes first semiconductor devices, and a first pad-level dielectric layer and embedding first bonding pads; and a second semiconductor die that includes second semiconductor devices, and a second pad-level dielectric layer embedding second bonding pads that includes a respective second pad base portion. Each of the first bonding pads includes a respective first pad base portion and a respective first metal alloy material portion having a higher coefficient of thermal expansion (CTE) than the respective first pad base portion. Each of the second bonding pads is bonded to a respective one of the first bonding pads.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: December 13, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar
  • Patent number: 11521984
    Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall of each vertical semiconductor channel in the memory opening fill structures. A metal-containing layer is deposited on physically exposed surfaces of the vertical semiconductor channel and the vertical semiconductor channel is crystallized using metal-induced lateral crystallization. Alternatively or additionally, cylindrical metal-semiconductor alloy regions can be formed around the vertical semiconductor channels to reduce contact resistance. A source contact layer can be formed in the source cavity.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 6, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar
  • Patent number: 11508833
    Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate and forming a plurality of core layers discretely arranged on the substrate. The method also includes forming a first sidewall spacer on a sidewall of a core layer of the plurality of core layers. In addition, the method includes removing the first sidewall spacer on a sidewall of at least one core layer; and forming a second sidewall spacer on the sidewall of the at least one core layer where the first sidewall spacer is removed. The first sidewall spacer is made of a material different from the second sidewall spacer.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 22, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Publication number: 20220362961
    Abstract: A miter saw has a base having a detent notch, a table rotatably connectable to the base, a pivoting assembly connected to the table, and a saw assembly supported by the pivoting assembly. The saw assembly has a blade movable downwardly for a cutting operation. A locking mechanism is disposed on the table. The locking mechanism is movable between an unlocked position and a locked position for selectively unlocking and locking the table for rotational movement relative to the base about the miter axis. The locking mechanism has a lock lever rotatably connected to the table. The lock lever has a handle for moving locking mechanism between the locked and unlocked positions. The saw also has a miter detent assembly for selectively engaging and disengaging the detent notch.
    Type: Application
    Filed: May 6, 2022
    Publication date: November 17, 2022
    Inventors: Torrey Rea LAMBERT, HuaMing YAO, Chao BU, Fei ZHOU
  • Patent number: 11487740
    Abstract: A system for managing database logging, the comprises a processor; and a user task executing in a database server process and executable by the processor, the user task to: receive in a database management system on a database server, a command to manipulate a portion of a database managed by the database management system; obtain a lock on the portion of the database; create a first log record in a first private log cache associated with the user task, the first log record recording a data manipulation to the portion of the database; enqueue the first log record to a queue; and release the lock on the portion of the database after copying the first log record to the queue.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: November 1, 2022
    Assignee: Sybase, Inc.
    Inventors: Fei Zhou, Sarika Iyer, Graham Ivey
  • Patent number: 11485697
    Abstract: Provided herein are compounds, compositions and method of using thereof to treat or prevent malaria.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: November 1, 2022
    Assignee: THE SCRIPPS RESEARCH INSTITUTE
    Inventors: Wil Joseph Andahazy, Arnab K. Chatterjee, Case W. Mcnamara, Federico C. Beasley, Anders Mikal Eliasen, Hank Michael James Petrassi, Jason T. Roland, Timothy Wells, Olga Vladimirovna Zatolochnaya, Fei Zhou, Peter G. Schultz, Anil Kumar Gupta
  • Patent number: 11482604
    Abstract: Semiconductor structures and fabrication methods thereof are provided. The method may include providing a substrate; forming a doped source/drain layer on a surface of the substrate; forming a channel pillar on the doped source/drain layer; forming a work function layer on side and top surfaces of the channel pillar; and forming a first isolation layer on the doped source/drain layer. The first isolation layer is on a portion of a sidewall surface of the work function layer. The method also includes forming a gate electrode layer on a surface of the work function layer and a surface of the first isolation layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 25, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11482420
    Abstract: Semiconductor device and fabrication method are provided. A plurality of spaced-apart fins is formed on a substrate. A dummy gate structure is formed across the fins over the substrate. A first interlayer dielectric layer is formed on the substrate and on a sidewall of the dummy gate structure, and a top of the first interlayer dielectric layer is lower than a top of the dummy gate structure and higher than a top of the fins. A cut-out opening, according to a cut-out pattern, is formed through the dummy gate structure and between adjacent fins. A second interlayer dielectric layer is formed on the first interlayer dielectric layer and fills in the cut-out opening.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: October 25, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11482539
    Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second end of the vertical semiconductor channel, and a source contact layer contacting the source region.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: October 25, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar
  • Publication number: 20220326160
    Abstract: The present disclosure provides a method for trapping molecules with optical fiber tweezers based on phase transition and crystallization and a method for detecting a Raman spectrum of a persistent organic pollutant, belonging to the technical field of surface-enhanced Raman spectroscopy. Based on quite different solubilities of a substance to be detected in different solvents, dissolved phase small molecules to be detected are transformed into large size crystalline phase molecules through the physical process of phase transition and crystallization. Further, effective trapping of molecules to be detected that are not prone to bonding to noble metal nanoparticles in the vicinity of the noble metal nanoparticles can be achieved by combining the physical process of phase transition and crystallization with the physical trapping technique using optical fiber tweezers, so that the sensitivity of surface-enhanced Raman scattering (SERS) spectrum detection is significantly improved.
    Type: Application
    Filed: July 28, 2021
    Publication date: October 13, 2022
    Applicant: Dongguan University of Technology
    Inventors: Fei Zhou, Ye Liu, Hongcheng Wang, Yadong Wei, Geng Zhang, Shaoqiang Zhang
  • Patent number: 11469241
    Abstract: An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: October 11, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Senaka Kanakamedala, Fei Zhou, Yao-Sheng Lee
  • Patent number: 11458155
    Abstract: An active ingredient complex is effective to treat, reduce the likelihood of developing, reduce the severity of, or ameliorate acute alcoholic liver damage or the symptoms of a hangover. In some embodiments, the active ingredient complex includes NADH (nicotinamide adenine dinucleotide (NAD)+hydrogen (H)), L-cysteine, dihydromyricetin (DHM), N-acetyl-cysteine (NAC), L-theanine, and buffered vitamin C, or pharmaceutically acceptable salts or derivative thereof. According to some embodiments, a pharmaceutical composition or dietary supplement may include the active ingredient complex and one or more pharmaceutically acceptable carriers, excipients, adjuvants and/or diluents.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: October 4, 2022
    Assignees: FULGENT LIFE INC., GUANG DONG HAI HE BIOTECHNOLOGY CO., LTD.
    Inventors: Yong Wu, Fei Zhou, Shengzhen Tang, Ke Wu, Shiliu Tian, Long Yi
  • Patent number: 11450687
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of ferroelectric memory elements surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers. Each of the ferroelectric memory elements includes a respective vertical stack of a first ferroelectric material portion and a second ferroelectric material portion that differs from the first ferroelectric material portion by at least one of a material composition and a lateral thickness.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: September 20, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Roshan Tirukkonda, Ramy Nashed Bassely Said, Senaka Kanakamedala, Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou
  • Patent number: 11448599
    Abstract: The present disclosure provides a method for trapping molecules with optical fiber tweezers based on phase transition and crystallization and a method for detecting a Raman spectrum of a persistent organic pollutant, belonging to the technical field of surface-enhanced Raman spectroscopy. Based on quite different solubilities of a substance to be detected in different solvents, dissolved phase small molecules to be detected are transformed into large size crystalline phase molecules through the physical process of phase transition and crystallization. Further, effective trapping of molecules to be detected that are not prone to bonding to noble metal nanoparticles in the vicinity of the noble metal nanoparticles can be achieved by combining the physical process of phase transition and crystallization with the physical trapping technique using optical fiber tweezers, so that the sensitivity of surface-enhanced Raman scattering (SERS) spectrum detection is significantly improved.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: September 20, 2022
    Assignee: Dongguan University Of Technology
    Inventors: Fei Zhou, Ye Liu, Hongcheng Wang, Yadong Wei, Geng Zhang, Shaoqiang Zhang
  • Publication number: 20220285386
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack and having lateral protrusions at levels of the electrically conductive layers, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner and located within volumes of the lateral protrusions. Each discrete memory element includes a vertical inner sidewall and a convex or stepped outer sidewall.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 8, 2022
    Inventors: Ramy Nashed Bassely SAID, Raghuveer S. MAKALA, Senaka KANAKAMEDALA, Fei ZHOU
  • Patent number: 11437478
    Abstract: A semiconductor device, its manufacturing method, and a radiation measurement method are presented, relating to semiconductor techniques. The semiconductor device includes: a substrate comprising a base area and a collector area adjacent to each other; a plurality of semiconductor fins on the substrate, wherein the plurality of semiconductor fins comprises at least a first semiconductor fin and a second semiconductor fin on the base area and separated from each other, the first semiconductor fin comprises an emission area adjacent to the base area, and the second semiconductor fin comprises a first region adjacent to the base area; a first gate structure on the second semiconductor fin; and a first source and a first drain at two opposite sides of the first gate structure and at least partially in the first region. Radiation in a semiconductor apparatus can be measured through this semiconductor device.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: September 6, 2022
    Inventor: Fei Zhou
  • Patent number: 11437364
    Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate including a first region of a first conductivity type and a second region of a second conductivity type opposite the first conductivity type, the first region and the second region being adjacent to each other and forming a pn junction in the semiconductor substrate, a semiconductor fin on the semiconductor substrate, and an electrode on the semiconductor fin. The pn junction in the semiconductor substrate has a relatively large area to prevent local hot spots from occurring when a current flows through the ESD protection device, thereby reducing performance degradation of a semiconductor device.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: September 6, 2022
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 11437270
    Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: September 6, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar, Senaka Krishna Kanakamedala, Fumitaka Amano, Genta Mizuno
  • Publication number: 20220278216
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and memory opening fill structures located in the memory opening and including a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner. A subset of the insulating layers a lower insulating sublayer, an upper insulating sublayer overlying the lower insulating sublayer, and a center insulating sublayer located between and in contact with the lower insulating sublayer and the upper insulating sublayer.
    Type: Application
    Filed: March 1, 2021
    Publication date: September 1, 2022
    Inventors: Xue Bai PITNER, Raghuveer S. MAKALA, Fei ZHOU, Senaka KANAKAMEDALA, Ramy Nashed Bassely SAID
  • Patent number: 11424265
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: August 23, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou, Rahul Sharangpani