Patents by Inventor Fen Huang
Fen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230381815Abstract: A method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form first protrusions and second protrusions, where a first diameter of each of the first protrusions is larger than a second diameter of each of the second protrusions; and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the first protrusions are disposed in the cavity.Type: ApplicationFiled: May 24, 2022Publication date: November 30, 2023Inventors: Chi-Yuan Shih, Shih-Fen Huang, Yan-Jie Liao, Wen-Chuan Tai
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Publication number: 20230372970Abstract: A method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form a plurality of first protrusions in a first region and a plurality of second protrusions in a second region, where a density of the plurality of first protrusions in the first region is different from a density of the plurality of second protrusions in the second region, and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the plurality of first protrusions and the plurality of second protrusions are disposed in the cavity.Type: ApplicationFiled: May 18, 2022Publication date: November 23, 2023Inventors: Yan-Jie Liao, Shih-Fen Huang, Chi-Yuan Shih
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Publication number: 20230375500Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Tawian Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Cheng Huang, Yi-Hsien Chang, Chin-Hua Wen, Chun-Ren Cheng, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Ching-Hui Lin, Sean Cheng, Hector Chang
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Publication number: 20230378251Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
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Patent number: 11821932Abstract: A partial discharge (PD) detection apparatus for gas-insulated equipment includes a photon collector, an optical splitter, a first photoelectric conversion module, an ultraviolet fluorescent crystal, a second photoelectric conversion module, and a signal processing module, where the ultraviolet fluorescent crystal is configured to convert a second optical radiation signal into an optical radiation signal of an ultraviolet fluorescence band, and the signal processing module is configured to calculate first apparent intensity based on a first voltage signal output by the first photoelectric conversion module, calculate second apparent intensity based on a second voltage signal output by the second photoelectric conversion module, and determine discharge intensity of the optical radiation based on a ratio of the second apparent intensity to the first apparent intensity. Technical solutions of the present disclosure are not affected by an unknown distance between a discharge position and a detection point.Type: GrantFiled: July 7, 2021Date of Patent: November 21, 2023Assignee: Wuxi Power Supply Branch of State Grid Jiangsu Electric Power Co., Ltd.Inventors: Jin Miao, Ping Chen, Yin Gu, Bin Fei, Xi Wu, Haiping Shen, Fen Huang, Zhaoyun Leng, Xinyang Zhou, Junfeng Wu, Jiefeng Wan
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Patent number: 11808731Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.Type: GrantFiled: December 28, 2020Date of Patent: November 7, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Cheng Huang, Yi-Hsien Chang, Chin-Hua Wen, Chun-Ren Cheng, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Ching-Hui Lin, Sean Cheng, Hector Chang
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Publication number: 20230317714Abstract: A method includes: forming a fin protruding from a substrate; implanting an n-type dopant in the fin to form an n-type channel region; implanting a p-type dopant in the fin to form a p-type channel region adjacent the n-type channel region; forming a first gate structure over the n-type channel region and a second gate structure over the p-type channel region; forming a first epitaxial region in the fin adjacent a first side of the first gate structure; forming a second epitaxial region in the fin adjacent a second side of the first gate structure and adjacent a first side of the second gate structure; and forming a third epitaxial region in the fin adjacent a second side of the second gate structure.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Kai-Qiang Wen, Shih-Fen Huang, Shih-Chun Fu, Chi-Yuan Shih, Feng Yuan
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Publication number: 20230314088Abstract: A heat dissipation device for a multipoint heat source includes an evaporator unit and a condenser unit. The evaporator unit includes a multi-channel duct. At least one narrow side of the multi-channel duct has a communication opening in communication with the bottom side of at least one tube of the condenser unit, and a wide side of the multi-channel duct is attached to the multipoint heat source so that a heat conduction medium can be circulated through the evaporator unit and the condenser unit while alternating between a liquid phase and a gaseous phase.Type: ApplicationFiled: June 30, 2022Publication date: October 5, 2023Inventors: CHENG-CHIEN WAN, CHENG-RUI WAN, CHUN-HSIEN SU, HUI-FEN HUANG, FONG JOU TU, CHI CHENG CHEN, CHUAN MENG WANG
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Publication number: 20230320227Abstract: A method for manufacturing a semiconductor structure is provided. The method may include several operations. A piezoelectric capacitor is formed over a substrate, wherein the piezoelectric capacitor includes a metal electrode. An intermediate layer is formed on the metal electrode, and is patterned using a first mask layer as a mask. A metal layer is formed on the intermediate layer, wherein the metal layer electrically connects to the metal electrode. The metal layer is patterned using a second mask layer, wherein the intermediate layer is within a coverage area of the metal layer from a top-view perspective after the patterning of the metal layer. A semiconductor structure thereof is also provided.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: CHING-HUI LIN, FU-CHUN HUANG, CHUN-REN CHENG, WEI CHUN WANG, CHAO-HUNG CHU, YI-HSIEN CHANG, PO-CHEN YEH, CHI-YUAN SHIH, SHIH-FEN HUANG, YAN-JIE LIAO, SHENG KAI YEH
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Publication number: 20230310523Abstract: The present invention discloses a method for maintaining or improving gastrointestinal condition, which includes: administering a lactic acid bacterial composition to a subject in need thereof, wherein the lactic acid bacterial composition comprises: a Lactobacillus paracasei ET-66 strain with a deposition number CGMCC 13514. The present invention also discloses a method for maintaining or improving gastrointestinal condition, which includes: administering a lactic acid bacterial fermentation composition to a subject in need thereof, wherein the lactic acid bacterial fermentation composition comprises: a fermentation product of a Lactobacillus paracasei ET-66 strain.Type: ApplicationFiled: April 22, 2022Publication date: October 5, 2023Inventors: Hsieh-Hsun HO, Wen-Yang LIN, Jui-Fen CHEN, Yi-Wei KUO, Jia-Hung LIN, Chi-Huei LIN, Ching-Wei CHEN, Yu-Fen HUANG
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Publication number: 20230302494Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a dielectric stack disposed on a substrate. The integrated chip structure further includes one or more piezoelectric ultrasonic transducers (PMUTs) and one or more capacitive ultrasonic transducers (CMUTs). The one or more PMUTs include a piezoelectric stack disposed within the dielectric stack over one or more PMUT cavities. The one or more CMUTs include electrodes disposed within the dielectric stack and separated by one or more CMUT cavities. An isolation chamber is arranged within the dielectric stack laterally between the one or more PMUTs and the one or more CMUTs. The isolation chamber vertically extends past at least a part of both the one or more PMUTs and the one or more CMUTs.Type: ApplicationFiled: June 6, 2022Publication date: September 28, 2023Inventors: Ching-Hui Lin, Yi-Hsien Chang, Chun-Ren Cheng, Fu-Chun Huang, Yi Heng Tsai, Shih-Fen Huang, Chao-Hung Chu, Po-Chen Yeh
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Patent number: 11769792Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a substrate comprising sidewalls that define a trench. A capacitor comprising a plurality of conductive layers and a plurality of dielectric layers that define a trench segment is disposed within the trench. A width of the trench segment continuously increases from a front-side surface of the substrate in a direction towards a bottom surface of the trench.Type: GrantFiled: July 8, 2021Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
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Publication number: 20230290688Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.Type: ApplicationFiled: March 11, 2022Publication date: September 14, 2023Inventors: Kai-Qiang Wen, Shih-Fen Huang, Shih-Chun Fu, Chi-Yuan Shih, Feng Yuan
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Publication number: 20230288369Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.Type: ApplicationFiled: April 10, 2023Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Hui LIN, Chun-Ren CHENG, Shih-Fen HUANG, Fu-Chun HUANG
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Patent number: 11757034Abstract: A high-voltage device includes a first frame-like isolation and a second frame-like isolation separated from each other, a first frame-like gate structure covering the first frame-like isolation, a second frame-like gate structure covering the second frame-like isolation, a first drain region enclosed by the first frame-like isolation, a second drain region enclosed by the second frame-like isolation, a first frame-like source region surrounding the first frame-like gate structure, a second frame-like source region surrounding the second frame-like gate structure, a first doped region surrounding the first and second frame-like gate structures, and a second doped region disposed between the first and second frame-like gate structures. The first and second drain regions, and the first and second frame-like source regions include a first conductivity type. The first and the second doped region include a second conductivity type.Type: GrantFiled: April 27, 2022Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hung-Sen Wang, Yun-Ta Tsai, Ruey-Hsin Liu, Shih-Fen Huang, Ho-Chun Liou
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Patent number: 11730058Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.Type: GrantFiled: May 16, 2019Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alexander Kalnitsky, Chun-Ren Cheng, Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yan-Jie Liao
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Patent number: 11717546Abstract: The present invention provides a method for promoting defecation, comprising administering a composition which includes: a fermentation powder of lactic acid bacteria and a physiologically acceptable excipient, diluent, or carrier. The fermentation powder includes: a fermentation product of lactic acid bacteria, the fermentation product is obtained by incubating lactic acid bacterial strains in a culture medium containing milk, milk powders, casein, soy beans, bean products, or whey, and the lactic acid bacterial strains include: a Lactobacillus salivarius subsp. salicinius AP-32 strain, a Lactobacillus plantarum LPL28 strain, a Lactobacillus acidophilus TYCA06 strain, and a Bifidobacterium longum subsp. infantis BLI-02 strain.Type: GrantFiled: May 3, 2021Date of Patent: August 8, 2023Assignee: GLAC BIOTECH CO., LTDInventors: Hsieh-Hsun Ho, Ching-Wei Chen, Yi-Wei Kuo, Yu-Fen Huang, Jui-Fen Chen, Cheng-Chi Lin
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Publication number: 20230242501Abstract: The present invention provides a novel compound for effectively preventing nerve damage and protecting nerves, and a preparation method thereof. Besides, the present invention also provides a pharmaceutical composition comprising the novel compound, and a use of the novel compound for preventing nerve damage and protecting nerves.Type: ApplicationFiled: January 28, 2022Publication date: August 3, 2023Inventors: LAIN-TZE LEE, HUI-PING TSAI, YI-WEN LIN, SHU-FEN HUANG, Shih-Hung LIU, Chin-Wei LIU, PI-TSAN HUANG, MEI-HUI CHEN
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Publication number: 20230246014Abstract: A semiconductor device is provided. The semiconductor device comprises a first semiconductor die comprising a first capacitor, and a second semiconductor die in contact with the first semiconductor die and comprises a diode. The first semiconductor die and the second semiconductor die are arranged along a first direction, and a diode is configured to direct electrons accumulated at the first capacitor to a ground.Type: ApplicationFiled: January 28, 2022Publication date: August 3, 2023Inventors: HSIN-LI CHENG, SHU-HUI SU, YU-CHI CHANG, YINGKIT FELIX TSUI, SHIH-FEN HUANG
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Patent number: 11659687Abstract: The present invention provides a stack-type vertical heat dissipation device comprising an evaporator unit and a condenser unit. The evaporator unit has a side configured for direct or indirect contact with, and thereby receiving heat from, a high-temperature device in order for the heat to convert a heat conduction medium inside the evaporator unit into a gaseous state. The condenser unit is stacked on a top side of a housing of the evaporator unit, and is provided therein with a flow channel that is in communication with the evaporator unit and allows passage of the heat conduction medium so that the heat conduction medium is able to return to the evaporator unit under a force of gravity after condensing from the gaseous state into a liquid state and thereby complete a thermal cycle.Type: GrantFiled: December 22, 2020Date of Patent: May 23, 2023Assignee: MAN ZAI INDUSTRIAL CO., LTD.Inventors: Cheng-Chien Wan, Cheng-Jui Wan, Chun-Hsien Su, Hui-Fen Huang