Patents by Inventor Fen Huang

Fen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11322580
    Abstract: In some embodiments, the present disclosure relates to a metal-insulator-metal (MIM) device. The MIM device includes a substrate, and a first and second electrode stacked over the substrate. A dielectric layer is arranged between the first and second electrodes. Further, the MIM device includes a titanium getter layer that is disposed over the substrate and separated from the dielectric layer by the first electrode. The titanium getter layer has a higher getter capacity for hydrogen than the dielectric layer.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yan-Jie Liao
  • Patent number: 11322609
    Abstract: A high-voltage device includes a substrate, a first well region disposed in the substrate, at least a first isolation, a frame-like gate structure over the first well region and covering a portion of the first isolation, a drain region in the first well region and separated from the frame-like gate structure by the first isolation, and a source region separated from the drain region by the first isolation and the frame-like gate structure. The first well region, the drain region and the source region include a first conductivity type, and the substrate includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Sen Wang, Yun-Ta Tsai, Ruey-Hsin Liu, Shih-Fen Huang, Ho-Chun Liou
  • Patent number: 11320395
    Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.
    Type: Grant
    Filed: June 14, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hui Lin, Chun-Ren Cheng, Jui-Cheng Huang, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Fu-Chun Huang
  • Patent number: 11289568
    Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Wen-Chuan Tai, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Anderson Lin, Fu-Chun Huang, Chun-Ren Cheng, Ivan Hua-Shu Wu, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Publication number: 20220078943
    Abstract: The present invention provides a stack-type vertical heat dissipation device comprising an evaporator unit and a condenser unit. The evaporator unit has a side configured for direct or indirect contact with, and thereby receiving heat from, a high-temperature device in order for the heat to convert a heat conduction medium inside the evaporator unit into a gaseous state. The condenser unit is stacked on a top side of a housing of the evaporator unit, and is provided therein with a flow channel that is in communication with the evaporator unit and allows passage of the heat conduction medium so that the heat conduction medium is able to return to the evaporator unit under a force of gravity after condensing from the gaseous state into a liquid state and thereby complete a thermal cycle.
    Type: Application
    Filed: December 22, 2020
    Publication date: March 10, 2022
    Inventors: Cheng-Chien WAN, Cheng-Jui WAN, Chun-Hsien SU, Hui-Fen HUANG
  • Patent number: 11255586
    Abstract: The present invention provides a parallel-connected condensation device, comprising a front condensation unit, a rear condensation unit, and a plurality of heat dissipation fins. The front condensation unit is parallel to the rear condensation unit. The heat dissipation fins is inserted into the front condensation unit and the rear condensation unit. The front condensation unit and the rear condensation unit comprise a plurality of confluence chambers. The confluence chambers are connected with each other to form a plurality of flow channels.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 22, 2022
    Assignee: MAN ZAI INDUSTRIAL CO., LTD.
    Inventors: Cheng-Chien Wan, Cheng-Jui Wan, Chun-Hsien Su, Hui-Fen Huang
  • Patent number: 11219841
    Abstract: The present invention provides a heat exchange device featuring gas-liquid separation, comprising an evaporator unit and a condenser unit. The condenser unit comprises a central main guide tube, a plurality of condensation tubes connected to the two lateral sides of the central main guide tube, and a heat dissipation fin assembly provided on a periphery of each condensation tube. The central main guide tube comprises a gaseous-phase confluence chamber and a liquid-phase confluence chamber. The gaseous-phase confluence chamber is provided in an upper portion of the central main guide tube and communicates with the gas outlet through a gaseous-phase connection tube, and the liquid-phase confluence chamber is provided in a lower portion of the central main guide tube and communicates with the evaporation chamber through a liquid-phase connection tube.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: January 11, 2022
    Assignee: MAN ZAI INDUSTRIAL CO., LTD.
    Inventors: Cheng-Chien Wan, Cheng-Jui Wan, Chun-Hsien Su, Hui-Fen Huang
  • Publication number: 20210401908
    Abstract: The present invention provides a composition for promoting defecation, which includes: a fermentation powder of lactic acid bacteria and a physiologically acceptable excipient, diluent, or carrier. The fermentation powder includes: a fermentation product of lactic acid bacteria, the fermentation product is obtained by incubating lactic acid bacterial strains in a culture medium containing milk, milk powders, casein, soy beans, bean products, or whey, and the lactic acid bacterial strains include: a Lactobacillus salivarius subsp. salicinius AP-32 strain, a Lactobacillus plantarum LPL28 strain, a Lactobacillus acidophilus TYCA06 strain, and a Bifidobacterium longum subsp. infantis BLI-02 strain.
    Type: Application
    Filed: May 3, 2021
    Publication date: December 30, 2021
    Inventors: Hsieh-Hsun HO, Ching-Wei CHEN, Yi-Wei KUO, Yu-Fen HUANG, Jui-Fen CHEN, Cheng-Chi LIN
  • Publication number: 20210401906
    Abstract: A composition for promoting defecation includes a cell culture of at least one lactic acid bacterial strain which is substantially free of cells. The least one lactic acid bacterial strain is selected from the group consisting of Lactobacillus salivarius subsp. salicinius AP-32, Bifidobacterium animalis subsp. lactis CP-9, and Lactobacillus acidophilus TYCA06, which are respectively deposited at the Bioresource Collection and Research Center (BCRC) under accession numbers BCRC 910437, BCRC 910645 and BCRC 910813. Also disclosed is a method for promoting defecation, including administering to a subject in need thereof an effective amount of the composition.
    Type: Application
    Filed: March 17, 2021
    Publication date: December 30, 2021
    Inventors: Hsieh-Hsun Ho, Ching-Wei Chen, Yi-Wei Kuo, Yu-Fen Huang, Cheng-Chi Lin
  • Publication number: 20210401907
    Abstract: The present invention provides a topical composition having a fermented product of lactic acid bacteria synbiotics as an active ingredient. The fermented product of lactic acid bacteria synbiotics is obtained by performing a fermenting step with lactic acid bacteria and a deactivating step on a fermenting substrate. The lactic acid bacteria are consisting of Lactobacillus salivarius subsp. salicinius AP-32, Bifidobacterium animalis subsp. lactis CP-9 and Lactobacillus acidophilus TYCA06. The fermenting substrate includes animal protein, plant protein and/or plant extracts. The aforementioned fermented product of lactic acid bacteria synbiotics can effectively inhibit the growth of Staphylococcus aureus and/or Propionibacterium acnes, and can be used in the topical composition.
    Type: Application
    Filed: March 18, 2021
    Publication date: December 30, 2021
    Inventors: Hsieh-Hsun Ho, Yi-Wei Kuo, Ching-Wei Chen, Yu-Fen Huang, Jia-Hung Lin
  • Publication number: 20210395985
    Abstract: An overflow valve cover includes a planar surface having a first surface and an opposing second surface. The planar surface includes a plurality of openings spaced apart along on the planar surface. An angled slat is positioned within each of the plurality of openings. A top edge of a collar is affixed to the circumference of the planar surface. A connector is positioned on the inner surface of the planar surface and extending away from the second surface.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 23, 2021
    Inventors: Sijiao Hsu, Mei-Na Fen Huang, Shao-Ting Huang, Montu Raval, Benny Chiang
  • Publication number: 20210389273
    Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.
    Type: Application
    Filed: June 14, 2020
    Publication date: December 16, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hui Lin, Chun-Ren Cheng, Jui-Cheng Huang, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Fu-Chun Huang
  • Publication number: 20210383972
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.
    Type: Application
    Filed: August 25, 2021
    Publication date: December 9, 2021
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Publication number: 20210376100
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.
    Type: Application
    Filed: August 18, 2021
    Publication date: December 2, 2021
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang
  • Publication number: 20210377439
    Abstract: Auto-focus method and a remote sensing satellite are disclosed. The satellite comprises at least a focal plane assembly (FPA) and a focus adjusting apparatus, the auto-focus method comprises: processing a point spread function (PSF) estimation to a multiple regions of a first image to generate multiple first estimated point spread functions; generating a first average point spread function according to the first estimated point spread functions; processing a Gaussian curve fitting to the first average PSF function and defining a first focus number; processing a PSF estimation to multiple regions of a second image to generate multiple second estimated PSF functions; generating a second average point spread function according to the second estimated point spread functions; processing a Gaussian curve fitting to the second average point spread function and defining a second focus number; and comparing the first focus number and the second focus number.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 2, 2021
    Applicant: National Applied Research Laboratories
    Inventors: Shiau-Jing Liu, Yu-Lin Tsai, Li-Fen Huang
  • Publication number: 20210343881
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a substrate comprising sidewalls that define a trench. A capacitor comprising a plurality of conductive layers and a plurality of dielectric layers that define a trench segment is disposed within the trench. A width of the trench segment continuously increases from a front-side surface of the substrate in a direction towards a bottom surface of the trench.
    Type: Application
    Filed: July 8, 2021
    Publication date: November 4, 2021
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Patent number: 11158739
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu, Kuang-Hsin Chen, Chih-Hsin Ko, Shih-Fen Huang
  • Publication number: 20210318073
    Abstract: The present invention provides a gravity high-efficiency heat dissipation apparatus comprising an evaporator and a condenser. The evaporator comprises a housing, an evaporation chamber arranged at the housing, and a skived structure arranged inside the evaporation chamber. The condenser comprises an upper circulating main pipe, a lower circulating main pipe and one or a plurality of condensation pipes having an upper opening and a lower opening fluidly connected to the upper circulating main pipe and the lower circulating main pipe respectively. The upper circulating main pipe is fluidly connected to an upper side of the evaporator via a first connecting pipe and is fluidly connected to an upper side of the evaporation chamber. The lower circulating main pipe is fluidly connected to one side of the evaporator via a second connecting pipe and is fluidly connected to the evaporation chamber. A circumferential side of each of the condensation pipes has one or a plurality of heat dissipation fins formed thereon.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 14, 2021
    Inventors: Cheng-Chien Wan, Cheng-Jui Wan, Chun-Hsien Su, Hui-Fen Huang
  • Patent number: 11124472
    Abstract: The present invention discloses a novel 3-aryl-2-propen-1-one series derivative and the synthesis processes thereof. Besides, the present invention also discloses the series derivative as a pharmaceutical composition and their use for promoting myocardial regeneration.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 21, 2021
    Assignee: GENHEALTH PHARMA CO., LTD.
    Inventors: Lain-Tze Lee, Hui-Ping Tsai, Shu-Fen Huang, Yi-Wen Lin, Pi-Tsan Huang, Ying-Ying Wu, Mei-Hui Chen, Li-Jie Hsu
  • Patent number: 11107630
    Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao