Abstract: An electromagnetic interference (EMI) gasket is provided that includes a resiliently-flexible and conductive outer shell, a cushioning element disposed in the outer shell, and at least one magnetic component disposed in the outer shell configured to magnetically couple to a conductive surface of an electronic device chassis.

Abstract: An angle adjustment mechanism for LED bar lighting includes a lamp body, two end covers arranged two ends of the lamp body along an axial direction thereof, two lamp frames respectively mounted on the two threading pipes, two wheel gears respectively fixed on the two lamp frames, two outer end caps fixed and covered on the two end covers, respectively, and at least two stopping plates respectively received in the two lamp frames. Each of the two end covers includes a threading pipe extending along the axial direction of the lamp body. Each of the two wheel gears includes a plurality of gear teeth taken along a radial direction thereof and rotating around the threading pipe. Each of the stopping plates provides at least one stopping tooth which is coupling to the gear teeth.

Abstract: A ultra-thin LED bar lights includes a bar house, a light module, a reflection film, a light guide plate, and a cover having a light transmittance less than 90%. An angle between the circuit board and the accessory placed board being larger than 80 degrees and less than 90 degrees. The light guide plate includes an incidence wall for receiving the emitted light of the light module, three reflective walls for reflecting light, and a diffusion surface contacting with the reflection film. A width of the diffusion surface of the light guide plate is between 3 times or 4 times the length or the maximum diameter of the LED chips and provides a plurality of light guide points thereon. The light guide points include a plurality of spaced apart circular dots, the total area of which is 50% to 55% of the total area of the diffusion surface.

Abstract: An angle adjustment mechanism for LED bar lighting includes a lamp body, two end covers arranged two ends of the lamp body along an axial direction thereof, two lamp frames respectively mounted on the two threading pipes, two wheel gears respectively fixed on the two lamp frames, two outer end caps fixed and covered on the two end covers, respectively, and at least two stopping plates respectively received in the two lamp frames. Each of the two end covers includes a threading pipe extending along the axial direction of the lamp body. Each of the two wheel gears includes a plurality of gear teeth taken along a radial direction thereof and rotating around the threading pipe. Each of the stopping plates provides at least one stopping tooth which is coupling to the gear teeth.

Abstract: An LED lighting assembly structure includes a lamp housing, and an end cap. The lamp housing includes at least one slot. The end cap includes a lug cap, at least one through-hole, and at least one reinforcing rib, and at least one fastener. The reinforcing rib and the through-hole are partially coincident with each other in a cross section perpendicular to the central axis of the through-hole. When the fastener is screwed into the through-hole and the slot, it may either cut into the reinforcing rib, or the reinforcing rib is pressed against the lug cap, or both the reinforcing rib is pressed against the lug cap and the fastener cuts into the reinforcing rib. As a result, the strength between the fastener and the lamp frame is improved, and it is possible to make the lamp house smaller and thinner, which is advantageous in reducing the volume of the entire lamp.

Abstract: The present disclosure relates to a dielectrically isolated semiconductor device and a method for manufacturing the same. The dielectrically isolated semiconductor device includes a semiconductor substrate, a first semiconductor layer above the semiconductor substrate, a second semiconductor layer above the first semiconductor layer, a semiconductor island in the second semiconductor layer, and a first dielectric isolation layer surrounding a bottom and sidewalls of the semiconductor island. The first dielectric isolation layer includes a first portion which is formed from a portion of the first semiconductor layer and extending along the bottom of the semiconductor island, and a second portion which is formed from a portion of the second semiconductor layer and extending along the sidewalls of the semiconductor island. The dielectrically isolated semiconductor devices needs no an SOI wafer and reduces manufacturing cost.

Abstract: A method for navigating is provided. The method comprises, in response to input on user equipment of a first member of a group who is travelling to a destination, one or more processors acquiring current position information of the user equipment of the first member. The method further includes one or more processors sending a first message to a server. The first message includes the current position information indicating an area where the first member was when the first message was sent. The first message is for directing a member of the group, who receives the first message when passing the area, to the same destination as the first member.

Abstract: The invention provides a MEMS device, semiconductor device, and method for manufacturing the same. The MEMS device comprises an enclosed cavity, the cavity having an inner wall extending in a first plane, the inner wall including a film deposition region for depositing a getter film, wherein one or more grooves are formed in the film deposition region, the angle between the sidewalls of the grooves and the first plane is more than 0° and less than 180°, and the getter film overlays the sidewall of the grooves. The invention can form the getter film in a smaller incident flux angle with a common sputtering, evaporation apparatus, that is, form the porous, high roughness getter.

Abstract: A method for navigating is provided. The method comprises, in response to input on user equipment of a first member of a group who is travelling to a destination, one or more processors acquiring current position information of the user equipment of the first member. The method further includes one or more processors sending a first message to a server. The first message includes the current position information indicating an area where the first member was when the first message was sent. The first message is for directing a member of the group, who receives the first message when passing the area, to the same destination as the first member.

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.

Abstract: An inverter and a power supply method thereof and an application thereof are provided. The inverter includes a DC-DC conversion circuit, an inverting circuit and an auxiliary power circuit. The DC-DC conversion circuit converts a DC input voltage into a DC bus voltage. The inverting circuit is configured to convert the DC bus voltage into an AC output voltage. The auxiliary power circuit is enabled in response to the DC input voltage, and the auxiliary power circuit generates a first auxiliary power for enabling the DC-DC conversion circuit after being enabled. The DC-DC conversion circuit is enabled in response to the first auxiliary power, and the DC-DC conversion circuit generates a second auxiliary power for enabling the inverting circuit after being enabled, such that the inverting circuit is enabled in response to the second auxiliary power and generates the AC output voltage.

Abstract: An LED strip light includes a printed circuit board, a plurality of LED chip, and a lens group. The lens group includes at least two spread light lenses. The spread light lenses include an optical axis, a light emitting surface, a central point of the light emitting surface, and a light incidence surface arranged at interval with the light emitting surface. A ligature between the central point of the light emitting surface and the central point of the light incidence surface is perpendicular to the light incidence surface and an angle between the ligature and the optical axis is equal to an angle between the light emitting surface and the light incidence surface to deflect the light emitted from the light emitting surface. The LED strip lights can avoid forming bad lighting regions which have dramatic light and shade contrast, and contribute to improve luminous efficacy of light source.

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.

Abstract: Synchronizing a Graphical User Interface (GUI) operation includes receiving operation information of the GUI operation performed on a first machine. The operation information includes object information and action information. The object information is in a first language and indicates a GUI object to which the GUI operation is directed. The action information indicates an action performed by the GUI operation on the GUI object. The object information in the first language is converted to object information in a second language. A GUI object in a GUI displayed on a second machine is identified according to the object information in the second language. The action indicated by the action information is performed on the identified GUI object.

Abstract: A method for forming a memory cell structure includes following steps. A substrate including at least a memory cell region defined thereon is provided, and a first gate stack is formed in the memory cell region. A first LDD implantation is performed to form a first LDD at one side of the first gate stack in the memory cell region, and the first LDD includes a first conductivity type. A second LDD implantation is performed to form a second LDD at one side of the first gate stack opposite to the first LDD in the memory cell region, and the second LDD includes the first conductivity type. The first LDD and the second LDD are different from each other.

Abstract: A multiple silicon trenches forming method and an etching mask structure, the method comprises: step S11, providing a MEMS sealing cap silicon substrate (100); step S12, forming n stacked mask layers (101, 102, 103) on the MEMS sealing cap silicon substrate (100), after forming each mask layer, photolithographing and etching the mask layer and all other mask layers beneath the same to form a plurality of etching windows (D1, D2, D3); step S13, etching the MEMS sealing cap silicon substrate by using the current uppermost mask layer and a layer of mask material beneath the same as a mask; step S14, removing the current uppermost mask layer; step S15, repeating the step S13 and the step S14 until all the n mask layers are removed.

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.

Abstract: An inverter and a power supply method thereof and an application thereof are provided. The inverter includes a DC-DC conversion circuit, an inverting circuit and an auxiliary power circuit. The DC-DC conversion circuit converts a DC input voltage into a DC bus voltage. The inverting circuit is configured to convert the DC bus voltage into an AC output voltage. The auxiliary power circuit is enabled in response to the DC input voltage, and the auxiliary power circuit generates a first auxiliary power for enabling the DC-DC conversion circuit after being enabled. The DC-DC conversion circuit is enabled in response to the first auxiliary power, and the DC-DC conversion circuit generates a second auxiliary power for enabling the inverting circuit after being enabled, such that the inverting circuit is enabled in response to the second auxiliary power and generates the AC output voltage.

Abstract: A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second S/D regions in the substrate beside the gate. The method includes performing a channel-initiated secondary electron (CHISEL) injection process to inject electrons to the charge-trapping structure.

Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.