Abstract: System and method for an all-digital audio receiver for a BTSC MTS audio signal or other composite signal that is FM modulated. A preferred embodiment comprises a digital FM demodulator for receiving an analog to digital quantized SIF signal and performing demodulation and outputting a composite audio signal, and a digital audio processor for decomposing the composite audio signal into at least the SAP, stereo and monaural signals for audio reproduction. In a preferred embodiment, the digital audio processor is a programmable digital signal processor. In a preferred embodiment, the digital FM demodulator and the digital audio processor are implemented as an integrated circuit. Methods for processing the audio signal using the digital processors of the invention are provided.

Abstract: An apparatus, system and method for clamping a video signal input to a coupling capacitor (215) for providing a clamping voltage. A charging current is applied to the capacitor (215) via an amplifier (225) having a first input (227) coupled with the capacitor output and a second input (226) coupled to a reference potential, the amplifier (225) is responsive to the capacitor output signal and the reference potential for providing the charging current to the capacitor (215). The current has a linearly varying magnitude which is proportional to a difference between the capacitor output and the reference potential.

Abstract: Systems and methods are provided for dividing two digital values. A look-up table provides a first output value in response to a value of an input signal. The first output value corresponds to a first estimate of a reciprocal for the value of the input signal. An approximation component provides a second output value corresponding to a second estimate of the reciprocal value for the value of the input signal as a function of the first output value and the value of the input signal. The look-up table is configured to provide the first output value within a predetermined error sufficient to enable the approximation component to improve the first estimate within a second predetermined error by the approximation component employing a single iteration of the function of the first output value and the value of the input signal.

Abstract: A clamping circuit disclosed herein has two modes of operation which include both a bottom level and mid-level clamping mode for clamping automatically onto the sync tip of a video signal and customizably clamping onto the front porch, back porch/pedestal or anywhere within the signal. The clamping circuit (400) includes a clamping capacitor (404) that couples to an automatic clamping circuit portion (405) to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage (Vref1) of a first clamping pulse signal during an automatic clamping mode of operation. The automatic clamping portion (405) connects to the customizable clamping circuit portion (411) to clamp any portion of the video input signal to a second predetermined reference voltage (Vref2) of a second clamping pulse signal during a customizable clamping mode of operation. A buffer (416) connects between the customizable clamping circuit portion and the output node of the clamping circuit.

Abstract: An aspect of the invention can be regarded an air bearing slider for use in a disk drive including a rotatable magnetic disk. The slider includes a leading side and a trailing side. The slider further includes opposing lateral sides extending between the leading and trailing sides. The slider further includes a transducer pad disposed adjacent the trailing side. The transducer pad includes a transducer for reading and writing data from and to the magnetic disk. The slider further includes a pair of pressurized side pads each respectively disposed laterally between the transducer pad and a respective one of the lateral sides. Each side pad includes a forward shallow etched surface, a trailing shallow etched surface extending from adjacent the trailing side toward the leading side, and a side pad air bearing surface disposed between and above the forward and trailing shallow etched surfaces.

Abstract: An image processing apparatus (200) for a charge coupled device including analog front end circuitry having optical black and offset correction, whereby the offset and optical black correction circuit is programmable. The present invention includes a first circuit (202, 204, 206, 208, 210) to sample the incoming optical black signal output from a CCD. This first circuit includes a correlated double sampler (202) coupled to a first programmable gain amplifier (204). An adder (206) connects between the first programmable gain amplifier (204) and a second gain amplifier (208) for adding in the optical black offset to the optical black signal input from the CCD. A second circuit (212, 214) includes a reverse programmable gain amplifier (212) connected to the output of the second programmable gain amplifier (208) to amplify the optical black level inversely proportional to the gain from the second programmable gain amplifier (208).

Abstract: A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is disclosed. According to one embodiment, the programmable gain amplifier (300a-300b) may include a capacitive switching circuit (304a-304b), a capacitive switching circuit (306a-306b), and an operational amplifier (302a-302b). Capacitive switching circuits (304a-304b and 306a-306b) may receive an analog input voltage through sample switches (308a-308b and 310a-310b). Capacitive switching circuit (304a-304b) receives an output from operational amplifier (302a-302b) through feedback switch (312a-312b). The programmable gain amplifier (300a-300b) may include a few additional unit capacitors which can allow larger gain ranges or more steps for a given range without a large increase in chip size.

Abstract: A method of operating a disk drive. The disk drive includes a disk having a disk surface, a slider disposable adjacent the disk surface, and a slider loading/unloading ramp for the slider. The method includes rotating the disk at a loading speed. The method further includes loading the slider from the loading/unloading ramp at a loading fly height above the disk surface. The method further includes rotating the disk at an operational speed greater than the loading speed. The method further includes operating the slider at an operational fly height above the disk surface less than the loading fly height above the disk surface. The method further includes rotating the disk at an unloading speed less than the operational speed. The method further includes unloading the slider from the disk to the loading/unloading ramp at an unloading fly height greater than the operational fly height.

Abstract: An apparatus, system and method for clamping a video signal input to a coupling capacitor (215) for providing a clamping voltage. A charging current is applied to the capacitor (215) via an amplifier (225) having a first input (227) coupled with the capacitor output and a second input (226) coupled to a reference potential, the amplifier (225) is responsive to the capacitor output signal and the reference potential for providing the charging current to the capacitor (215). The current has a linearly varying magnitude which is proportional to a difference between the capacitor output and the reference potential.

Abstract: A shunt-shunt feedback current to voltage converter (60) including a compensating current (22) provided to the output of the amplifier (12) which mirrors the input current (14) advantageously removing the loading effects of the feedback resistor (Rf) to the amplifier (12). A current steering DAC (40) is utilized in conjunction with a plurality of polarity control switches (62) to provide either a source current or a sink current to the amplifier input, and a complementary sink current or source current, respectively, to the output of the amplifier such that the amplifier (12) does not provide any current to the feedback resistor. Thus, DC gain of the amplifier is maintained. The current steering DAC (40) provides a matched source current and sink current to achieve this architecture.

Abstract: The invention concerns methods for modulating the &bgr;-adrenergic pathway. In particular, the invention concerns methods for counteracting a pathologic change, such as, for example, a loss in &bgr;-adrenergic sensitivity, in the &bgr;-adrenergic signal transduction pathway by administering an effective amount of a compound capable of inhibiting TGF-&bgr; signaling through a TGF-&bgr; receptor.

Abstract: An image processing apparatus for charge coupled device (CCD) and video inputs in a digital camera or for a digital camcorder is disclosed which provides optical black and offset correction for CCD inputs. A sampling circuit, including correlated double sampler (CDS) (402) and programmable gain amplifier (450), samples the image input signal and the video input signal. CDS (402) includes a single-ended amplifier (404) and a differential amplifier (406). The single-ended amplifier (404) functions such that it is only operable during an CCD signal input; otherwise, the single-ended amplifier (404) is bypassed such that a video signal is only sampled by the differential amplifier (406). For CCD signals, the single-ended amplifier (404) samples the reference level of the pixel and holds it during the video interval. The differential amplifier (404) samples both the output of the single ended amplifier (404) and the video level of the same pixel.

Abstract: An apparatus for generating a digital signal representative of an analog signal includes two signal conversion devices, each having an analog signal section coupled with an input locus and a digital signal section coupled between the analog signal section and an output locus. The signal conversion devices receive sampled analog signals that are phase-offset by a first phase difference. Two feedback devices are each coupled between the output locus of one signal conversion device and the analog signal section of the other signal conversion device to convey feedback signals that are phase-offset by a second phase difference. The first phase difference and the second phase difference cooperate to affect power density spectrum of a resultant digital output signal at at least one predetermined frequency. The resultant digital output signal is a summing of a digital output signals presented by the two signal conversion devices at their output loci.

Abstract: A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit (22 and 24) for receiving an input signal and a symmetry circuits (205 and 210) advantageously configured to provide an output signal exhibiting a symmetrical rising and falling edge waveform in response to the received input signal. An integrated power source (Is) provides current to a common node (N1) in which current is advantageously steered to each half circuit (22, 205 and 24, 210) to reduce voltage variation on the common node during voltage transition of the input signal, hence, reducing current fluctuation from the current source.

Abstract: A clamping circuit disclosed herein has two modes of operation which include both a bottom level and mid-level clamping mode for clamping automatically onto the sync tip of a video signal and customizably clamping onto the front porch, back porch/pedestal or anywhere within the signal. The clamping circuit (400) includes a clamping capacitor (404) that couples to an automatic clamping circuit portion (405) to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage (Vref1) of a first clamping pulse signal during an automatic clamping mode of operation. The automatic clamping portion (405) connects to the customizable clamping circuit portion (411) to clamp any portion of the video input signal to a second predetermined reference voltage (Vref2) of a second clamping pulse signal during a customizable clamping mode of operation. A buffer (416) connects between the customizable clamping circuit portion and the output node of the clamping circuit.

Abstract: An apparatus for generating a digital signal representative of an analog signal includes two signal conversion devices, each having an analog signal section coupled with an input locus and a digital signal section coupled between the analog signal section and an output locus. The signal conversion devices receive sampled analog signals that are phase-offset by a first phase difference. Two feedback devices are each coupled between the output locus of one signal conversion device and the analog signal section of the other signal conversion device to convey feedback signals that are phase-offset by a second phase difference. The first phase difference and the second phase difference cooperate to affect power density spectrum of a resultant digital output signal at at least one predetermined frequency. The resultant digital output signal is a summing of a digital output signals presented by the two signal conversion devices at their output loci.

Abstract: A shunt-shunt feedback current to voltage converter (60) including a compensating current (22) provided to the output of the amplifier (12) which mirrors the input current (14) advantageously removing the loading effects of the feedback resistor (Rƒ) to the amplifier (12). A current steering DAC (40) is utilized in conjunction with a plurality of polarity control switches (62) to provide either a source current or a sink current to the amplifier input, and a complementary sink current or source current, respectively, to the output of the amplifier such that the amplifier (12) does not provide any current to the feedback resistor. Thus, DC gain of the amplifier is maintained. The current steering DAC (40) provides a matched source current and sink current to achieve this architecture.

Abstract: A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is disclosed. According to one embodiment, the programmable gain amplifier (300a-300b) may include a capacitive switching circuit (304a-304b), a capacitive switching circuit (306a-306b), and an operational amplifier (302a-302b). Capacitive switching circuits (304a-304b and 306a-306b) may receive an analog input voltage through sample switches (308a-308b and 310a-310b). Capacitive switching circuit (304a-304b) receives an output from operational amplifier (302a-302b) through feedback switch (312a-312b). The programmable gain amplifier (300a-300b) may include a few additional unit capacitors which can allow larger gain ranges or more steps for a given range without a large increase in chip size.

Abstract: A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is disclosed. According to one embodiment, the programmable gain amplifier (300a-300b) may include a capacitive switching circuit (304a-304b), a capacitive switching circuit (306a-306b), and an operational amplifier (302a-302b). Capacitive switching circuits (304a-304b and 306a-306b) may receive an analog input voltage through sample switches (308a-308b and 310a-310b). Capacitive switching circuit (304a-304b) receives an output from operational amplifier (302a-302b) through feedback switch (312a-312b). The programmable gain amplifier (300a-300b) may include a few additional unit capacitors which can allow larger gain ranges or more steps for a given range without a large increase in chip size.

Abstract: A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit (22 and 24) for receiving an input signal and a symmetry circuits (205 and 210) advantageously configured to provide an output signal exhibiting a symmetrical rising and falling edge waveform in response to the received input signal. An integrated power source (Is) provides current to a common node (N1) in which current is advantageously steered to each half circuit (22, 205 and 24, 210) to reduce voltage variation on the common node during voltage transition of the input signal, hence, reducing current fluctuation from the current source.