Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a cap layer over the gate stack. The semiconductor device structure includes a protective layer over the cap layer. A lower portion of the protective layer extends into the cap layer. The semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.

Abstract: Apparatus, methods and systems for light tape. The light tape may include a first segment. The light tape may include a first array of light emitting diodes (“LEDs”). The first array of LEDs may be disposed along the first segment. The first array of LEDs may emit light in a first direction. The light tape may include a second array of LEDs. The second array of LEDs may be disposed along the first segment. The second array of LEDs may emit light in a second direction. The light tape may include a first extension extending from the first segment. The first extension may be physically connected to a second extension extending from a second segment. The first extension may form a joint when connected to the second extension. The joint may include at least one LED disposed on each of the first extension and the second extension.

Abstract: The disclosure provides communication methods and apparatuses. One example method includes that the first access network device obtains a correspondence between the first terminal apparatus and the second terminal apparatus. After obtaining a data packet, the first access network device sends a same data packet to the first terminal apparatus and the second terminal apparatus based on the correspondence, so that the first terminal apparatus and the second terminal apparatus transmit the same data packet to the slave station device.

Abstract: The present invention relates to the technical field of clamping equipment and discloses a clamping mechanism and a clamping apparatus.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A voltage regulator includes a first portion with a first converter phase and a second portion with second and third converter phases, and a compensation inductor. The first converter phase receives an input voltage and provides an output voltage through a first inductor. The second converter phase receives the input voltage and provides the output voltage through a first primary winding of a first coupled inductor. The first coupled inductor includes a first secondary winding magnetically coupled to the first primary winding. The third converter phase receives the input voltage and provides the output voltage through a second primary winding of a second coupled inductor. The second coupled inductor includes a second secondary winding magnetically coupled to the second primary winding. The compensation inductor, first secondary winding, and of the second secondary winding are coupled in series between a ground plane.

Abstract: A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.

Abstract: A semiconductor package includes a carrier plate, a photonic integrated circuit chip, an electronic integrated circuit chip and an interposer substrate. The carrier plate has a notch and a first surface and a second surfaces opposite to the first surface, and the notch extends from the first surface toward the second surface. The photonic integrated circuit chip is disposed within the notch. The electronic integrated circuit chip is disposed on the first surface of the carrier plate. The photonic integrated circuit chip and the electronic integrated circuit chip are disposed on the carrier through the interposer substrate.

Abstract: A method for manufacturing an electronic device is provided. The method includes providing a first substrate. The method further includes forming a bank layer on the first substrate. The bank layer includes a bank wall and a first opening, and the first opening adjacent to the bank wall. The method further includes forming a light conversion layer in the first opening. The method further includes forming a spacer on the bank wall. The method further includes providing a second substrate. The method further includes transferring a plurality of electronic units to the second substrate. The method further includes overlapping the first substrate and second substrate, so that the spacer is located between the first substrate and the second substrate.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A display panel and a formation method thereof, and a display apparatus are provided in the present disclosure. The method includes providing a base substrate; forming an array layer on a side of the base substrate; forming a light-emitting structure layer on a side of the array layer away from the base substrate, where the light-emitting structure layer includes a plurality of light-emitting units; and forming a light-blocking layer on a side of the light-emitting structure layer away from the base substrate, where the light-blocking layer includes a black matrix and openings. Before forming the openings, the method further includes forming a first inorganic layer between the light-emitting structure layer and the light-blocking layer, where the first inorganic layer at least includes first sub-portions; and a vertical projection of a first sub-portion on the base substrate overlaps a vertical projection of a corresponding opening on the base substrate.

Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.

Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Abstract: An electromagnetic switch having a display light is disclosed. The electromagnetic switch includes a housing; an electromagnetic unit in the housing; a contact unit in the housing; a button unit having a top seat, a power-on button and a power-off button, wherein the top seat is connected to the housing in a snap-fit manner, the power-on button and the power-off button are slidably connected to the top seat, respectively; a display light that is fixedly connected between the top seat and the power-on button and has a circuit board, a light-emitting member, and two conductive wires. The two conductive wires are connected to the contact unit. When the power-on button is pressed to turn on the electricity, the light-emitting member will emit light to remind the operator. When the power supply is not normal, the electromagnetic switch is powered off to remind the operator of abnormal power supply.

Abstract: This disclosure provides methods, components, devices and systems for signal generation. Some aspects more specifically relate to frequency-selective digital predistortion signal generation. In some examples, the method alters an input signal to produce a frequency-selected linear output signal of a power amplifier. For frequency-selective pre-distortion signal generation, a digital pre-distortion circuit suppresses the non-linear distortion at a specific band using Volterra kernels of a Volterra series model and a shiftable finite impulse response (FIR). The shiftable FIR can filter a particular portion of the signal's frequency, and the Volterra kernels can capture the non-linear memory effects of the input signals and output signals of the power amplifier. Upon refinement of the Volterra kernel coefficients, the Volterra series model can produce a compensation signal.

Abstract: A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a cap layer over the gate stack. The semiconductor device structure includes a protective layer over the cap layer, wherein a lower portion of the protective layer extends into the cap layer. The semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.

Abstract: A defect inspection system is disclosed, and comprises a linear light source, N number of cameras, a display device, a tag reader, and a modular electronic device, in which the linear light source, the cameras and the modular electronic device are used for conducting a defect inspection of an article. On the other hand, the display device, the tag reader and the modular electronic device are adopted for conducting in production of at least one labeled example. Therefore, the modular electronic device is allowed to apply a machine learning process to an image classifier under using a training dataset containing the labeled examples, thereby producing at least one new defect recognition model or updating the existing defect recognition model.

Abstract: A method and a system for identifying authenticity of an electronic component is disclosed. The method may include obtaining chip data of an electronic component; extracting feature information of the chip data for reducing noise of the chip data; providing the feature information of the chip data to a trained deep learning model; and providing a user with an authenticity indication for the electronic component based on an output of the deep learning model. Other aspects, embodiments, and features are also claimed and described.

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.