Abstract: A semiconductor device includes a first transistor located in a first region and a second transistor located in a second region. The first transistor includes first and second channel members vertically stacked above the substrate, and a first gate dielectric layer having a first portion wrapping around the first channel member and a second portion wrapping around the second channel member. The second transistor includes third and fourth channel member vertically stacked above the substrate and a second gate dielectric layer having a first portion wrapping around the third channel member and a second portion wrapping around the fourth channel member. The first and second channel members are thicker than the third and fourth channel members. A vertical distance between the first and second portions of the first gate dielectric layer is larger than a vertical distance between the first and second portions of the second gate dielectric layer.

Abstract: Systems and methods of testing integrated circuits independent of chip package configuration include or utilize a socket configured to receive a device under test (DUT), wherein the socket includes a plurality of input pins and a plurality of output pins, and wherein the DUT includes a plurality of device pins; a wireless communication device configured to wirelessly transmit information on the DUT to a server device operating a machine learning (ML) model, and wirelessly receive response data generated by the ML model from the server device, the response data including at least one of a pin configuration information of the DUT or a timing configuration information of the DUT; and a switch array configured to route respective ones of the plurality of device pins to corresponding ones of the plurality of output pins based on the response data.

Abstract: A flexible and intuitive system is disclosed, and is disposed to be coupled to at least one camera, at least one robotic arm and a host electronic device of an AVI system. During a normal operation of the system, a configuration parameter setting of the AVI system can be completed after at least one time of robotic arm setting operation and at least one time of camera setting operation are conducted. After that, a plurality of article images acquired from a specific article by the camera are upload to a remote electronic device by the system, such that the remote electronic device utilizes the article images to update (re-train) a defect recognition model. Consequently, after the system integrates the defect recognition model into a defect recognition program that is installed in the host electronic device, the AVI system is hence configured for conducting an appearance inspection of the article.

Abstract: A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.

Abstract: An automatic target image acquisition and calibration system for application in a defect inspection system is disclosed. During the defect inspection system working normally, the automatic target image acquisition and calibration system is configured to find a recognition structure from an article under inspection, and then determines a relative position and a relative 3D coordinate if the article. Therefore, a robotic arm is controlled to carry a camera to precisely face each of a plurality of inspected surfaces of the article, such that a plurality of article images are acquired by the camera. It is worth explaining that, during the defect inspection of the article, there is no need to modulate an image acquiring height and an image acquiring angle of the camera and an illumination of a light source.

Abstract: An information handling system may include one or more information handling resources and a power system comprising a plurality of voltage regulator phases each configured to generate an output voltage at its output from an input voltage, the plurality of voltage regulator phases distributed among a plurality of voltage regulator banks comprising at least a first voltage regulator bank and a second voltage regulator bank. The information handling system may also include a power controller configured to monitor a temperature imbalance between the first voltage regulator bank and the second voltage regulator bank and control electrical currents delivered by the plurality of voltage regulator phases as a function of the temperature imbalance in order to minimize the temperature imbalance.

Abstract: A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A display panel includes a base substrate; an array layer, on a side of the base substrate; a light-emitting structure layer, on a side of the array layer away from the base substrate, the light-emitting structure layer including a plurality of light-emitting units; a touch control layer, on the side of the light-emitting structure layer away from the base substrate; a first inorganic layer, on a side of the touch control layer away from the base substrate; and color filter parts, on a side of the first inorganic layer away from the base substrate.

Abstract: An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.

Abstract: A package structure and manufacturing method thereof. The package structure includes first package assembly and a second package assembly. The first package assembly includes a first dielectric layer, a first chip and a first conductive structure. The first chip is disposed in the first dielectric layer, and a first electrical connection surface of the first conductive structure is exposed on a first bonding surface of the first dielectric layer. The second package assembly includes a second dielectric layer, a second chip and a second conductive structure. The second chip is disposed in the second dielectric layer, and a second electrical connection surface of the second conductive structure is exposed on a second bonding surface of the second dielectric layer. The first bonding surface is directly bonded to the second bonding surface, and the first electrical connection surface is directly bonded to the second electrical connection surface.

Abstract: A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

Abstract: A wireless charging apparatus is disclosed. The wireless charging apparatus comprises a transmitting coil assembly, a heat conduction stand, and a heat conduction housing; wherein the transmitting coil assembly comprises a magnetic sheet and a transmitting coil, wherein the transmitting coil is put on the magnetic sheet. The heat generated by the transmitting coil assembly during charging can be transferred to the heat conduction stand and then further to the heat conduction housing to dissipate heat, so as to reduce the temperature of the wireless charging apparatus.

Abstract: A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a cap layer over the gate stack. The semiconductor device structure includes a protective layer over the cap layer. A lower portion of the protective layer extends into the cap layer. The semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.

Abstract: Apparatus, methods and systems for light tape. The light tape may include a first segment. The light tape may include a first array of light emitting diodes (“LEDs”). The first array of LEDs may be disposed along the first segment. The first array of LEDs may emit light in a first direction. The light tape may include a second array of LEDs. The second array of LEDs may be disposed along the first segment. The second array of LEDs may emit light in a second direction. The light tape may include a first extension extending from the first segment. The first extension may be physically connected to a second extension extending from a second segment. The first extension may form a joint when connected to the second extension. The joint may include at least one LED disposed on each of the first extension and the second extension.

Abstract: The disclosure provides communication methods and apparatuses. One example method includes that the first access network device obtains a correspondence between the first terminal apparatus and the second terminal apparatus. After obtaining a data packet, the first access network device sends a same data packet to the first terminal apparatus and the second terminal apparatus based on the correspondence, so that the first terminal apparatus and the second terminal apparatus transmit the same data packet to the slave station device.

Abstract: The present invention relates to the technical field of clamping equipment and discloses a clamping mechanism and a clamping apparatus.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A voltage regulator includes a first portion with a first converter phase and a second portion with second and third converter phases, and a compensation inductor. The first converter phase receives an input voltage and provides an output voltage through a first inductor. The second converter phase receives the input voltage and provides the output voltage through a first primary winding of a first coupled inductor. The first coupled inductor includes a first secondary winding magnetically coupled to the first primary winding. The third converter phase receives the input voltage and provides the output voltage through a second primary winding of a second coupled inductor. The second coupled inductor includes a second secondary winding magnetically coupled to the second primary winding. The compensation inductor, first secondary winding, and of the second secondary winding are coupled in series between a ground plane.