Abstract: A semiconductor device includes an interface layer on a substrate, a gate dielectric layer on the interface layer, and a work function metal layer on the gate dielectric layer. An interface between the interface layer and the gate dielectric layer has a concentration of a dipole-inducing element. The semiconductor device also includes an oxygen blocking layer on the work function metal layer and a metal fill layer on the oxygen blocking layer.

Abstract: A synchronization method and an apparatus are provided to meet a time precision requirement of an industrial factory in a scenario in which a mobile network is connected to an Ethernet network. In an embodiment, a first device determines seventh timestamp information by using timestamp information of receiving and sending packets in a mobile network, so that a second device calculates a time offset between the first device and the second device based on the seventh timestamp information and time points of receiving and sending packets in an Ethernet network, to perform time synchronization. In the method, impact of a transmission delay between the first device and the second device can be avoided, so that a time precision requirement of an industrial factory can be met in a scenario in which the mobile network is connected to the Ethernet network.

Abstract: A method includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and merging between vertically adjacent portions of the first gate dielectric layer, and a second dipole layer surrounding the second gate dielectric layer and merging between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; after the removing of the first dipole layer, conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.

Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Abstract: The disclosure provides communication methods and apparatuses. One example method includes that the first access network device obtains a correspondence between the first terminal apparatus and the second terminal apparatus. After obtaining a data packet, the first access network device sends a same data packet to the first terminal apparatus and the second terminal apparatus based on the correspondence, so that the first terminal apparatus and the second terminal apparatus transmit the same data packet to the slave station device.

Abstract: A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

Abstract: Monolithic power stage (Pstage) packages and methods for using same are provided that may be implemented to provide lower thermal resistance/enhanced thermal performance, reduced noise, and/or smaller package footprint than conventional monolithic Pstage packages. The conductive pads of the disclosed Pstage packages may be provided with a larger surface area for contacting respective conductive layers of a mated PCB to provide a more effective and increased heat transfer away from a monolithic Pstage package. In one example, the increased heat transfer away from the monolithic Pstage package results in lower monolithic Pstage package operating temperature and increased power output.

Abstract: Disclosed in an embodiment of the present disclosure is a wireless power transmission apparatus, including a coil, accommodation bodies, and magnet units, wherein the accommodation bodies are arranged at intervals around the coil; and the magnet unit is disposed in the accommodation body in a movable manner. Owing to a constrained activity of the magnet unit, the wireless power transmission apparatus in the technical solution of the embodiment of the present disclosure can adapt to a plurality of wireless power receiving or transmitting apparatuses, thereby having good practicability, and improving the use experience of a user and the charging efficiency.

Abstract: Methods, systems, and apparatus for clock synchronization are provided. In one aspect, a clock synchronization method includes: receiving, by a terminal and from an access network device, information about N clock domains, determining, by the terminal, M clock domains that are associated with the terminal and that are in the N clock domains, and separately performing, by the terminal, clock synchronization with clock sources of the M clock domains based on information about the M clock domains. Information about a clock domain includes first time information and a clock domain number of the clock domain. The first time information includes a time of a clock source of the clock domain when the access network device sends the information about the clock domain. The clock domain number identifies the clock domain. N is an integer greater than 1, and M is an integer greater than 1.

Abstract: An array substrate and a display screen, where the array substrate includes a display area and a wiring area located on one side of the display area, the wiring area includes an upper wiring layer and a lower wiring layer laminated with the upper wiring layer, the upper wiring layer and the lower wiring layer are separated by an insulating layer group, the insulating layer group includes an insulating sub-layer and an insulating organic compensator formed on the insulating sub-layer, the insulating organic compensator is configured to compensate for at least part of a recess on an upper surface of the insulating sub-layer.

Abstract: A power stage includes a power converter having high- and low-side switches, a driver circuit that drives the switching power converter based upon a PWM signal, and a current sensing circuit that detects a low-side current level on the low-side switch, and provides a current level signal that includes the low-side current level. The power stage turns on the low-side switch at a first time, and estimates a first low-side current level at the first time. In estimating the first low-side current level, the power stage detects a second low-side current level at a second time while the low-side switch is turned on, the second time being after the first time, and detects a third low-side current level at a third time while the low-side switch is turned on, wherein the third time is after the second time. The first low-side current level is estimated based upon the second and third low-side current levels.

Abstract: A wavelength selective filter comprises a multi-layered structure alternately having a low refractive index layer and a high refractive index layer, a periodic structure layer facing the low refractive index layer of the multi-layered structure, the low refractive index layer having a refractive index between 1.30 and 1.60 and a thickness between 100 nm and 800 nm, the high refractive index layer having a refractive index between 1.70 and 2.20 and a thickness between 30 nm and 100 nm, and in a plane perpendicular to a thickness direction of the periodic structure layer, the multi-layered structure layer having a periodic structure made of metal or semiconductor.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

Abstract: A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

Abstract: Apparatus, methods and instructions for disinfecting air. The apparatus may include, and the methods may involve, a fixture. The fixture may include a germicidal light source. The fixture may include a fan. The fan may circulate air through a volume into which the germicidal light source propagates germicidal light. The light source may be configured to emit, upward from a horizontal plane, a beam that, absent reflection off an environmental object, does not cross the horizontal plane. The apparatus may include a shield that prevents light from the light source from crossing the horizontal plane. The sensor may face upward from the horizontal plane. The sensor may face downward from the horizontal plane.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

Abstract: An information transmission method and a related device are provided. The method includes: determining, by a base station, to send downlink information to P user equipments of at least one user equipment within a first time period; generating, by the base station, an indication field according to the determined P user equipments, where the indication field includes M bits, each of the at least one user equipment is corresponding to K bits of the M bits, the K bits are used to indicate whether the corresponding user equipment needs to receive and read the downlink information sent by the base station within the first time period, K is a positive integer greater than 1 and less than M, and P is an integer greater than or equal to 0; and sending, by the base station, the indication field to the at least one user equipment.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; performing a first treatment by introducing a trap-repairing element on the first and second dielectric layers; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; and forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions.