Abstract: A first module is configured to, based on an input sample, determine a first duty cycle. A second module is configured to, based on a battery voltage and the first duty cycle, determine a second duty cycle. A third module is configured to: set a scalar value based on at least one of a battery current, an amplitude of the input sample, the second duty cycle, and an output voltage; and generate a start signal at a rate equal to a predetermined rate multiplied by the scalar value. A fourth module is configured to set a third duty cycle based on the second duty cycle and the scalar value. A fifth module is configured to generate a PWM output based on the start signal and the third duty cycle. A sixth module is configured to apply power to gates of FETs of a voltage converter based on the PWM output.

Abstract: A cutting device for use in a drill bit has a body including an ultrahard material. The body has a top surface, a front surface, and at least one lateral surface adjacent the top surface. The lateral surface is oriented at a surface angle relative to the top surface between 30 and 150 degrees. One or more locking features are located on the lateral surface.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

Abstract: A parallel optical scanning inspection device, comprising a light source unit, an interference unit, a beam splitting unit, an optical path adjustment unit, a plurality of scanning units and a receiving unit. The light source unit provides initial light to an interference unit. The interference unit divides the initial light into reference light and sampling light. The beam splitting unit splits the sampling light into a plurality of sampling light beams. The optical path adjustment unit adjusts the plurality of sampling light beams into scanning light beams with different optical paths. Each of the scanning units receives one of the scanning light beams. A sample is scanned by the scanning light beams such that each of the scanning units receives detection light reflected or scattered from different positions of the sample. The receiving unit receives and coheres the reference light and the detection light, respectively, to generate optical information.

Abstract: A semiconductor device includes a stack of semiconductor layers vertically arranged above a semiconductor base structure, a gate dielectric layer having portions each surrounding one of the semiconductor layers, and a gate electrode surrounding the gate dielectric layer. Each portion of the gate dielectric layer has a top section above the respective semiconductor layer and a bottom section below the semiconductor layer. The top section has a top thickness along a vertical direction perpendicular to a top surface of the semiconductor base structure; and the bottom section has a bottom thickness along the vertical direction. The top thickness is greater than the bottom thickness.

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

Abstract: The invention relates to a carburizing bearing steel and a preparation method thereof. The carburizing bearing steel of the invention comprises: 0.18˜0.24 wt % of C, 0.4˜0.6 wt % of Cr, 0.20˜0.40 wt % of Si, 0.40˜0.70 wt % of Mn, 1.6˜2.2 wt % of Ni, 0.15˜0.35 wt % of Mo, 0.001˜0.01 wt % of S, 0.001˜0.015 wt % of P, 0˜0.20 wt % of Nb, 0˜0.20 wt % of V and the remaining is iron, wherein the contents of Nb and V are not 0 at the same time. In the invention, an appropriate amount of Nb and V is added in combination with other elements so as to refine the grain size, inhibit the generation of large granular carbides in the steel during carburization and improve the uniformity of the microstructure of steel materials, thus further enhancing the contact fatigue life of the carburizing bearing steel.

Abstract: A semiconductor device includes an interface layer on a substrate, a gate dielectric layer on the interface layer, and a work function metal layer on the gate dielectric layer. An interface between the interface layer and the gate dielectric layer has a concentration of a dipole-inducing element. The semiconductor device also includes an oxygen blocking layer on the work function metal layer and a metal fill layer on the oxygen blocking layer.

Abstract: A synchronization method and an apparatus are provided to meet a time precision requirement of an industrial factory in a scenario in which a mobile network is connected to an Ethernet network. In an embodiment, a first device determines seventh timestamp information by using timestamp information of receiving and sending packets in a mobile network, so that a second device calculates a time offset between the first device and the second device based on the seventh timestamp information and time points of receiving and sending packets in an Ethernet network, to perform time synchronization. In the method, impact of a transmission delay between the first device and the second device can be avoided, so that a time precision requirement of an industrial factory can be met in a scenario in which the mobile network is connected to the Ethernet network.

Abstract: The disclosure provides communication methods and apparatuses. One example method includes that the first access network device obtains a correspondence between the first terminal apparatus and the second terminal apparatus. After obtaining a data packet, the first access network device sends a same data packet to the first terminal apparatus and the second terminal apparatus based on the correspondence, so that the first terminal apparatus and the second terminal apparatus transmit the same data packet to the slave station device.

Abstract: A method includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and merging between vertically adjacent portions of the first gate dielectric layer, and a second dipole layer surrounding the second gate dielectric layer and merging between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; after the removing of the first dipole layer, conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.

Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Abstract: A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

Abstract: Monolithic power stage (Pstage) packages and methods for using same are provided that may be implemented to provide lower thermal resistance/enhanced thermal performance, reduced noise, and/or smaller package footprint than conventional monolithic Pstage packages. The conductive pads of the disclosed Pstage packages may be provided with a larger surface area for contacting respective conductive layers of a mated PCB to provide a more effective and increased heat transfer away from a monolithic Pstage package. In one example, the increased heat transfer away from the monolithic Pstage package results in lower monolithic Pstage package operating temperature and increased power output.

Abstract: Disclosed in an embodiment of the present disclosure is a wireless power transmission apparatus, including a coil, accommodation bodies, and magnet units, wherein the accommodation bodies are arranged at intervals around the coil; and the magnet unit is disposed in the accommodation body in a movable manner. Owing to a constrained activity of the magnet unit, the wireless power transmission apparatus in the technical solution of the embodiment of the present disclosure can adapt to a plurality of wireless power receiving or transmitting apparatuses, thereby having good practicability, and improving the use experience of a user and the charging efficiency.

Abstract: An array substrate and a display screen, where the array substrate includes a display area and a wiring area located on one side of the display area, the wiring area includes an upper wiring layer and a lower wiring layer laminated with the upper wiring layer, the upper wiring layer and the lower wiring layer are separated by an insulating layer group, the insulating layer group includes an insulating sub-layer and an insulating organic compensator formed on the insulating sub-layer, the insulating organic compensator is configured to compensate for at least part of a recess on an upper surface of the insulating sub-layer.

Abstract: Methods, systems, and apparatus for clock synchronization are provided. In one aspect, a clock synchronization method includes: receiving, by a terminal and from an access network device, information about N clock domains, determining, by the terminal, M clock domains that are associated with the terminal and that are in the N clock domains, and separately performing, by the terminal, clock synchronization with clock sources of the M clock domains based on information about the M clock domains. Information about a clock domain includes first time information and a clock domain number of the clock domain. The first time information includes a time of a clock source of the clock domain when the access network device sends the information about the clock domain. The clock domain number identifies the clock domain. N is an integer greater than 1, and M is an integer greater than 1.

Abstract: A power stage includes a power converter having high- and low-side switches, a driver circuit that drives the switching power converter based upon a PWM signal, and a current sensing circuit that detects a low-side current level on the low-side switch, and provides a current level signal that includes the low-side current level. The power stage turns on the low-side switch at a first time, and estimates a first low-side current level at the first time. In estimating the first low-side current level, the power stage detects a second low-side current level at a second time while the low-side switch is turned on, the second time being after the first time, and detects a third low-side current level at a third time while the low-side switch is turned on, wherein the third time is after the second time. The first low-side current level is estimated based upon the second and third low-side current levels.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.