Abstract: A debugger enhancement provides a debug-task-provider interface whose implementation includes routines designed to support debugging of programs that contain tasks written for a specific programming model. Task creation hierarchies, individual task properties, resource dependencies, synchronization dependencies, and other information can be made accessible during debugging, through a model-independent interface. In a multithreaded environment, a mapping between tasks and threads is also available.

Abstract: A battery system includes batteries; a voltage detector linking batteries and detecting batteries' voltage; an equalizer linking batteries and fine-tuning their charging/discharging efficiency; a battery protection board on which there is a MCU used to receive signals from the voltage detector for characteristic differences between batteries balanced by the equalizer and batteries with similar charging and discharging efficiency; a digital interface connected between the MCU and an upper-level control system as one interface of signal transmission.

Abstract: In one aspect of the invention, the method of forming a TFT array panel includes forming a patterned first conductive layer on a substrate, forming a gate insulating layer on the patterned first conductive layer and the substrate, forming a patterned semiconductor layer on the gate insulating layer, forming a patterned second conductive layer, forming a patterned passivation layer on the patterned second conductive layer and the substrate, and forming a patterned transparent conductive layer on the patterned passivation layer.

Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes: a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over the base portion of the fin structure. The collector portion is a first doped region including a first type dopant, and is coupled with a first terminal for electrically biasing the collector portion. The emitter portion is a second doped region including the first type dopant, and is coupled with a second terminal for electrically biasing the emitter portion. The base portion is a third doped region including a second type dopant opposite the first type, and is coupled with a third terminal for electrically biasing the base portion. The gate structure is coupled with a fourth terminal for electrically biasing the gate structure, such that the gate structure controls a path of current through the base portion.

Abstract: A drag-and-tag authentication apparatus includes an electronic device, a setting mechanism and an authentication mechanism. The electronic device includes a processor, a display electrically connected to the processor, an operation unit electrically connected to the processor, and a power supply electrically connected to the processor. The setting mechanism is electrically connected to the processor and includes first and second selection units operable for selecting literal and graphic items. The authentication mechanism is electrically connected to the processor and includes literal items and graphic items. Some of the literal items can be located and define a polygonal region. Some of the graphic items can be located and covered by the polygonal region for authentication.

Abstract: A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for fabricating the device based on the mask pattern. Next, a plurality of scattering bar reference sets is applied to the image simulation model so as to generate a plurality of simulation images, respectively. Further, a portion of the simulation images are selected to be a plurality of candidate layouts according to a screening criterion. Next, one of the candidate layouts is determined to be a pattern layout according to a selection rule, and the scattering bar reference set corresponding to the pattern layout is determined to be a scattering bar rule of the mask pattern.

Abstract: A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.

Abstract: A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.

Abstract: A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer with a first state, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer with a second state, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region of the substrate. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer.

Abstract: An optical compensation film includes an optical film and a retardation film. The optical film provides a plate retardation in the direction of thickness (Rth), while the retardation film is disposed on the optical film. The retardation film includes first retarders and second retarders, wherein the first retarders are disposed on at least partial areas of the optical film and provide a first planar retardation (Ro1); the second retarders are disposed on partial areas of the optical film but outside the first retarders and provide a second planar retardation (Ro2) and the first planar retardation (Ro1) is different from the second planar retardation (Ro2). The above-mentioned optical compensation film is capable of compensating the displays for different display areas in a liquid crystal display panel. In addition, the present invention also provides a fabricating method of optical compensation film.

Abstract: A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.

Abstract: A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.

Abstract: An optical compensation film includes an optical film and a retardation film. The optical film provides a plate retardation in the direction of thickness (Rth), while the retardation film is disposed on the optical film. The retardation film includes first retarders and second retarders, wherein the first retarders are disposed on at least partial areas of the optical film and provide a first planar retardation (Ro1); the second retarders are disposed on partial areas of the optical film but outside the first retarders and provide a second planar retardation (Ro2) and the first planar retardation (Ro1) is different from the second planar retardation (Ro2). The above-mentioned optical compensation film is capable of compensating the displays for different display areas in a liquid crystal display panel. In addition, the present invention also provides a fabricating method of optical compensation film.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.

Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process.

Abstract: Thin film transistors and fabrication methods thereof. A gate is formed overlying a portion of a substrate. A first vanadium oxide layer formed overlying the gate and the substrate. A gate-insulating layer is formed overlying the first vanadium oxide layer. A semiconductor layer is formed on a portion of the gate-insulating layer. A source and a drain are formed on a portion of the semiconductor layer.

Abstract: An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

Abstract: An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.