Abstract: Various embodiments can be used to process packages or documents that contain markup language describing one or more documents. Markup language descriptions can be processed to identify certain objects that reoccur or are repeated in the markup language description. If a re-occurring or repeating object is encountered in the markup language description, a resource dictionary can be used to catalog such objects and, an associated object model can include, from the resource dictionary, references to a re-occurring or repeating object. By using the resource dictionary as such, memory resources can be conserved when an in-memory representation of the object model is built.

Abstract: An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

Abstract: An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.

Abstract: An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.

Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.

Abstract: A field effect transistor including a substrate which includes, a fin structure, the fin structure having a top surface. The field effect transistor further including an isolation in the substrate and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the fin structure and the isolation structure. The S/D recess cavity includes a lower portion, the lower portion further includes a first strained layer, a first dielectric film and a second dielectric film, wherein the first strained layer is disposed between the first dielectric film and the second dielectric film. The S/D recess cavity further includes an upper portion including a second strained layer overlying the first strained layer, wherein a ratio of a height of the upper portion to a height of the lower portion ranges from about 0.8 to about 1.2.

Abstract: Idle processor cores can be used to compile methods that are likely to be executed by a program based on profile data that is captured during one or more previous executions. Methods that are determined by the profile data to be likely to be used can be compiled eagerly on one or more background threads. Transparency can be achieved by ensuring that module load order is not altered because of the background threads by recording the state of loaded modules after each profiled compilation, persisting that data, and waiting to eagerly compile a method until the method to be compiled and all its dependencies has been loaded by the executing program.

Abstract: A method of fabricating a semiconductor device includes providing a substrate having a fin disposed thereon. A gate structure is formed on the fin. The gate structure interfaces at least two sides of the fin. A stress film is formed on the substrate including on the fin. The substrate including the stress film is annealed. The annealing provides a tensile strain in a channel region of the fin. For example, a compressive strain in the stress film may be transferred to form a tensile stress in the channel region of the fin.

Abstract: The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.

Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.

Abstract: An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.

Abstract: A dual view display structure and a method for producing the same are provided. First, a display panel is provided. Then, a patterned barrier layer is formed on a transparent substrate. The transparent substrate with the patterned barrier layer is attached to the display panel. Because there is a gap between the display panel and the patterned barrier layer, a liquid transparent material is injected into the gap to form a transparent material layer to fill the gap. The invention can not only increase the viewing angles of the dual view display, but also increase the production yield.

Abstract: Various embodiments can be used to process packages or documents that contain markup language describing one or more documents. Markup language descriptions can be processed to identify certain objects that reoccur or are repeated in the markup language description. If a re-occurring or repeating object is encountered in the markup language description, a resource dictionary can be used to catalog such objects and, an associated object model can include, from the resource dictionary, references to a re-occurring or repeating object. By using the resource dictionary as such, memory resources can be conserved when an in-memory representation of the object model is built.

Abstract: A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.

Abstract: A touch display capable of switching modes is disclosed in the present invention. The touch display includes a touch panel, an image controller electrically connected to the touch panel, a switch, and a touch signal processor electrically connected to the touch panel, the image controller and the switch. The touch panel generates a touch signal according to a plurality of blocks triggered on the touch panel. The image controller receives an image signal outputted from a host and drives the touch panel to display a corresponding image. The switch can be used to switch the touch signal processor to a first operating mode or a second operating mode. The touch signal processor receives the touch signal, and transmits the touch signal to the image controller or to the host according to the mode switched by the switch.

Abstract: Rheometry apparatus comprises a block of substantially rigid material having an external surface and at least a first internal flow channel, the first internal flow channel being arranged inside the block and substantially in a plane and the block further comprising a plurality of holes, each hole communicating with the first internal flow channel at a respective position along the first internal flow channel and extending from the respective position to said external surface so as to provide access to the first internal flow channel from the external surface, the plurality of holes comprising a first hole communicating with a first said position, for connection to pumping means to drive fluid flow along said first internal flow channel, a second hole communicating with a second position and in which a sensor may be located to measure a property of fluid at the second position, and a third hole communicating with a third position and in which a sensor may be located to measure a property of fluid at the third

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process.

Abstract: A hierarchical battery-management system mainly comprises a monitoring and equalizing module, an intermediary module, and a decision and communication module. The monitoring and equalizing module electrically couples with the battery cells, the intermediary modules electrically couple with the monitoring and equalizing module and the decision and communication module. The decision and communication module electrically couples with a power system or an electronic/electrical apparatus, and a hierarchical management structure constructed by the intermediary module to screen data and to transmit meaningful cell data to meet real time managing requirements of the large battery set.

Abstract: A brushless direct current (BLDC) motor has a 3-phase winding 20 and six stator teeth 14, 15 with alternate stator teeth 14 being wound and the remaining stator teeth 15 being left unwound. The winding 20 has three legs, one for each phase and each leg has one coil 22 wound about one of the stator teeth 14. Each leg has a first end A,B,C, arranged to receive electrical power and a second end X,Y,Z, which is connected to the second end of the other legs to form a star connection 24. Selected stator teeth have grooves in a face thereof dividing those teeth into a plurality of stator poles. The motor may be used to drive a fuel pump for an internal combustion engine, typically for a vehicle.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate and a 3D structure disposed over the substrate. The semiconductor device further includes a dielectric layer disposed over the 3D structure, a WFMG layer disposed over the dielectric layer, and a gate structure disposed over the WFMG layer. The gate structure traverses the 3D structure and separates a source region and a drain region of the 3D structure. The source and drain region define a channel region therebetween. The gate structure induces a stress in the channel region.