Abstract: Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: A photomask and a method of manufacturing a photomask are provided. According to an embodiment, a method includes: providing a substrate; depositing a reflective layer including molybdenum layers and silicon layers over the substrate; depositing a capping layer over the reflective layer; depositing an absorption layer over the capping layer; and performing a treatment to form a border region including molybdenum silicide in the reflective layer.

Abstract: In various examples, a three-dimensional (3D) data processing pipeline for autonomous systems and applications is presented. Systems and methods are disclosed for 3D point cloud data processing fused with video analysis applications. Using the systems and methods described herein, processing of 3D data may be performed in different multimedia frameworks, allowing a user to use common libraries and/or to implement custom libraries on top of the existing system design. As a result, conventional 2D video processing may be combined with 3D data processing, to allow for data representing a flat 2D world to represent a rich 3D world. In this way, the fused 3D depth and/or range data with 2D camera image data allows for perception and/or vision that is more powerful, accurate, and precise.

Abstract: A photomask and a method of manufacturing a photomask are provided. According to an embodiment, a method includes: providing a substrate; depositing a reflective layer over the substrate; depositing a capping layer over the reflective layer; depositing an absorption layer over the capping layer; and treating the reflective layer by a laser beam to form a border region. The borderer region has a reflectivity less than about 0.1%.

Abstract: A method includes: forming a fin protruding from a substrate; implanting an n-type dopant in the fin to form an n-type channel region; implanting a p-type dopant in the fin to form a p-type channel region adjacent the n-type channel region; forming a first gate structure over the n-type channel region and a second gate structure over the p-type channel region; forming a first epitaxial region in the fin adjacent a first side of the first gate structure; forming a second epitaxial region in the fin adjacent a second side of the first gate structure and adjacent a first side of the second gate structure; and forming a third epitaxial region in the fin adjacent a second side of the second gate structure.

Abstract: A fail-safe on-board unit, a movable device, and a control method for a vehicle which will automatically and reliably broadcast a distress signal to a rescue center in the event of accident includes in the on-board unit a first subscriber identity module (SIM), a second SIM, a main processor, a modem, a radio frequency (RF) switch module, and an antenna module with several antennas. The main processor selects the first SIM and / or the second SIM to make a call to generate a baseband signal, and outputs the baseband signal to the modem, the modem converts the baseband signal into an RF signal, and outputs the RF signal to the RF switch module to transmit outward via one or more antennas of the antenna module. The on-board unit has a wider network coverage to ensure higher success rate of emergency calls.

Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

Abstract: An color aligning method of display for a computer system having a processing unit, a display and a server includes determining, by the server, a color information file of the display according to a related information of the display; downloading, by the processing unit, the color information file of the display from the server; and enabling, by the processing unit, the color information file according to a preset mode of the display.

Abstract: An apparatus and method for efficient image optimized image stitching. For example, one embodiment of an apparatus comprises: feature search area identification circuitry/logic to narrow down a feature search area based on possible overlap between two image frames; feature detection circuitry/logic to identify a plurality of feature points in a first image frame of the two image frames; feature matching circuitry/logic to map one or more of the plurality of feature points from the first image frame to corresponding feature points in the right image frame; image frame stitching and blending circuitry/logic to stitch the first image frame and second image frame based on the mapping of the feature points between the two image frames and to blend a portion of the first image frame with a portion of the second image frame.

Abstract: A circuit. In one aspect, the circuit includes a first power stage including a first switch having a first gate terminal, a first drain terminal and a first source terminal, and a second switch having a second gate terminal, a second drain terminal and a second source terminal, the first source terminal coupled to the second drain terminal, and a second power stage including a third switch having a third gate terminal, a third drain terminal and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the third source terminal coupled to the fourth drain terminal, where the second power stage is coupled in parallel to the first power stage such that the first drain terminal is couped to the third drain terminal and the second source terminal is connected to the fourth source terminal.

Abstract: Various strained channel transistors are disclosed herein. An exemplary semiconductor device includes a substrate and a fin structure disposed over the substrate. The fin structure includes a first epitaxial layer disposed on the substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The second epitaxial layer includes a relaxed transversal stress component and a longitudinal compressive stress component, and the third epitaxial layer has uni-axial strain. A gate structure is disposed on a channel region of the fin structure, such that the gate structure interposes a source region and a drain region of the fin structure.

Abstract: Method, systems and apparatuses may provide for technology that identifies first data and second data to be stored in a data storage. Each of the first data and the second data are in a first data format. Some technology may also interleave the first data with the second data. The interleaved first and second data are in a second data format. The second data format is different from the first data format.

Abstract: Systems, apparatuses and methods may provide technology for optimizing an inference neural network model that performs asymmetric quantization by generating a quantized neural network, wherein model weights of the neural network are quantized as signed integer values, and wherein an input layer of the neural network is configured to quantize input values as unsigned integer values, generating a weights accumulation table based on the quantized model weights and a kernel size for the neural network, and generating an output restoration function for an output layer of the neural network based on the weights accumulation table and the kernel size. The technology may also perform per-input channel quantization. The technology may also perform mixed-precision auto-tuning.

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: An uplink transmission method includes receiving a first message that is used to configure a first uplink resource. The method also includes performing uplink transmission on the first uplink resource. The first uplink resource includes at least a first part and a second part in a first time period, a phase deviation of uplink transmission between the first part and the second part falls within a first threshold range, or a power deviation of uplink transmission between the first part and the second part falls within a second threshold range. The first time period is a duration between a start time and an end time of the first uplink resource in a first time length, or a duration between a start time and an end time of the first uplink resource in a first transmit opportunity.

Abstract: The presently disclosed subject matter relates to devices, systems, and methods of producing an improved fluid flow assembly and liquid/gas diffusion layer in solid polymer electrolyte electrochemical cells. In one aspect, a fluid flow assembly for a polymer electrolyte water electrolyzer includes a flow field having an inlet, an outlet, and a plurality of discrete lands arranged within the flow field. A liquid/gas diffusion layer is positioned in communication with the flow field between the inlet and the outlet, the liquid/gas diffusion layer having a solid substrate through which a plurality of pores is formed. The disclosed bipolar plate flow field and liquid/gas diffusion layer could work together or separately with other types of porous transport layers or bipolar plates to enhance the water/gas transport. In these configurations, the lands can be arranged and configured such that the plurality of pores are substantially unobstructed by the lands.

Abstract: The presently disclosed subject matter relates to devices, systems, and methods for fabricating a solid polymer electrolyte electrode assembly are provided. One or more electrode for a solid polymer electrolyte electrode assembly includes a porous substrate configured as a liquid/gas diffusion layer and an ionomer-free catalyst coated on the substrate.

Abstract: A photolithography exposure of a photoresist coating on a semiconductor wafer uses an optical projection system to form a latent image. The photolithography exposure further uses a mask with a set of multiple pattern focus (MPF) marks. Each MPF mark of includes features having different critical dimension (CD) sizes. The latent image is developed to form a developed photoresist pattern. Dimension sizes are measured of features of the developed photoresist pattern corresponding to the features of the MPF marks having different CD sizes. A spatial focus map of the photolithography exposure is constructed based on the measured dimension sizes. To determine the focal distance at an MPF mark, ratios or differences may be determined between the measured dimension sizes corresponding to the features of the MPF marks having different CD sizes, and the focal distance at the location of the MFP mark constructed based on the determined ratios or differences.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a semiconductor substrate having a first surface and a first optical coupler disposed on the first surface of the semiconductor substrate. The first optical coupler includes a first surface facing away from the first surface of the semiconductor substrate and a first lateral surface connected to the first surface of the first optical coupler. The first surface of the first optical coupler and the first lateral surface of the optical coupler define an angle greater than 90 degrees. A method of manufacturing a semiconductor device package is also disclosed.