Patents by Inventor Feng Yuan

Feng Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9983473
    Abstract: A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: May 29, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Yi-Jie Chen, Feng-Yuan Chiu, Ying-Chou Cheng, Kuei-Liang Lu, Ya-Hui Chang, Ru-Gun Liu, Tsai-Sheng Gau
  • Publication number: 20180130887
    Abstract: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width.
    Type: Application
    Filed: January 4, 2018
    Publication date: May 10, 2018
    Inventors: Yu-Min Lin, Kuo-Lung Fang, Feng-Yuan Gan
  • Patent number: 9953885
    Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng Yuan, Tsung-Lin Lee, Hung-Ming Chen, Chang-Yun Chang
  • Patent number: 9887444
    Abstract: A filter capable of adjusting frequency and bandwidth for dynamically setting at least one of the filter center frequency and bandwidth includes a first movable member, a second movable member, an upper casing, a lower casing, multiple conductive clamping members, a cavity and a driving module. The first and second movable members have multiple first and second lugs formed on the first and second boards respectively. The upper and lower casings have multiple upper and lower openings corresponsive to the first lugs and the second lugs respectively. The conductive clamping members are corresponsive to the upper openings and the lower openings. The cavity has multiple chambers and multiple connecting portions. The driving module changes the position of the first movable member to determine the filter center frequency and the position of the second movable member to determine the bandwidth.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 6, 2018
    Assignee: UNIVERSAL MICROWAVE TECHNOLOGY, INC
    Inventors: Yu-Cheng Chen, Jen-Ti Peng, Jung-Chin Hsu, Feng-Yuan Huang, Guo-Hong Li
  • Publication number: 20180034915
    Abstract: A method and system for generating an automated Internet connection is provided. The method includes receiving from a first communication hardware device of a first user, a first telephone number and a first Internet protocol (IP) address. A second telephone number and a second Internet protocol (IP) address are received from a second communication hardware device of a second user. A request for connecting the first communication hardware device to the second communication hardware device via an Internet connection is received and it is determined that the second communication hardware device is currently connected the first communication hardware device. The request is transmitted to the second communication hardware device. Based on the second user approving the request, the second IP address is automatically transmitted to the first communication device and a secure private Internet link between the first communication hardware device and the second communication hardware device is generated.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 1, 2018
    Inventors: Tao Liu, Han Yang Xu, Xiao Yun Xu, Jun Feng Yuan
  • Publication number: 20170358648
    Abstract: Various strained channel transistors are disclosed herein. An exemplary semiconductor device includes a substrate and a fin structure disposed over the substrate. The fin structure includes a first epitaxial layer disposed on the substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The second epitaxial layer includes a relaxed transversal stress component and a longitudinal compressive stress component, and the third epitaxial layer has uni-axial strain. A gate structure is disposed on a channel region of the fin structure, such that the gate structure interposes a source region and a drain region of the fin structure.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 14, 2017
    Inventors: MARK VAN DAL, GERBEN DOORNBOS, GEORGIOS VELLIANITIS, TSUNG-LIN LEE, FENG YUAN
  • Publication number: 20170346350
    Abstract: A permanent magnet motor and a home appliance including the permanent magnet motor are provided. The permanent magnet motor includes a stator and a rotor rotatable relative to the stator. The rotor includes a rotary shaft, a rotor core fixed to the rotary shaft, a commutator fixed to the rotary shaft and adjacent the rotor core, and a rotor winding wound around poles of the rotor core and electrically connected with the commutator. The stator includes a cylindrical housing, a permanent magnet mounted to an inner surface of the housing, and brushes in sliding contact with the commutator. A ratio of an outer diameter of the rotor core to an outer diameter of the housing is 60% to 85%, and a wire diameter of the rotor winding is 0.12 mm to 0.23 mm. The present invention can provide higher output power without increasing sizes of the motor.
    Type: Application
    Filed: May 22, 2017
    Publication date: November 30, 2017
    Inventors: Xiao Ping LV, Ching Hang Alan LEUNG, Wei Feng YUAN
  • Publication number: 20170341021
    Abstract: The present invention provides a waste-liquid processing device, comprising: a first processing device and a mixing device, wherein the first processing device is provided with a first purifying unit for processing waste liquid from a waste liquid source to produce a purified liquid. The mixing device is used for mixing the purified liquid with a chlorine dioxide solution. The present invention also provides an air-pollution treatment device, comprising the waste-liquid processing device and a gas processing device. The gas processing device comprises an air extracting unit, a gas purifying unit, a gas-liquid separation unit, and an exhausting unit.
    Type: Application
    Filed: May 24, 2017
    Publication date: November 30, 2017
    Inventors: FENG-YUAN TSENG, JIUN-HONG TSENG, JUI-PO TSENG, TE-HUI LIU, TE-JUNG LIU
  • Publication number: 20170338976
    Abstract: A method for obtaining a port path and an apparatus to improve a network capacity, where the method includes receiving, by a controller, a request message from a first server, where the request message requests port path information, and the port path information includes a port that a logical link from the first server to a second server passes through, obtaining, by the controller, a first absolute port path (APP) and a second APP according to network topology information, where the first APP includes a port that a logical link from a root node to the first server passes through, and the second APP includes a port that a logical link from the root node to the second server passes through, obtaining, by the controller, the port path information according to the first APP and the second APP, and sending the port path information to the first server.
    Type: Application
    Filed: August 7, 2017
    Publication date: November 23, 2017
    Inventors: Yang Wang, Feng Yuan, Liang Xia, Guang Chen, Duoliang Fan
  • Publication number: 20170314150
    Abstract: The present invention discloses a flow generating device for an electrolytic cell, comprising a plurality of helical circulation channels and a coolant supply unit. The plurality of helical circulation channels are configured to be provide at an outer peripheries of an electrolytic cell that is for producing gaseous chlorine dioxide, and each of the helical circulation channels is provided with at least one coolant inlet. The coolant supply unit is for providing a coolant. When a coolant from the coolant supply unit is flowed into the helical circulation channels through the coolant inlet, flow is generated in an electrolyte in the electrolytic cell. The generated flows agitate the electrolyte thereby the voids appearing during the generation of the gaseous chlorine dioxide can be quickly occupied, so as to promote the efficiency of the electrolysis.
    Type: Application
    Filed: April 27, 2017
    Publication date: November 2, 2017
    Inventors: TE-HUI LIU, FENG-YUAN TSENG, JIUN-HONG TSENG, JUI-PO TSENG
  • Publication number: 20170308498
    Abstract: A display device is provided, which includes a display panel, a controlling unit, a first universal serial bus (USB) interface, a signal configuration unit, and a second universal serial bus interface. The controlling unit controls the display panel to display an image frame according to display data. When the first USB interface is connected to an external device, the signal configuration unit receives the display data and USB data via the first USB interface, and transmits the display data to the controlling unit. The second USB interface receives the display data from the controlling unit and receives the USB data from the signal configuration unit, so as to transmit the display data and the USB data to another display device via an USB cable.
    Type: Application
    Filed: June 22, 2016
    Publication date: October 26, 2017
    Inventor: Feng-Yuan Chen
  • Patent number: 9761666
    Abstract: The present disclosure provides a semiconductor device with a strained SiGe channel and a method for fabricating such a device. In an embodiment, a semiconductor device includes a substrate including at least two isolation features, a fin substrate disposed between and above the at least two isolation features, and an epitaxial layer disposed over exposed portions of the fin substrate. According to one aspect, the epitaxial layer may be disposed over a top surface and sidewalls of the fin substrate. According to another aspect, the fin substrate may be disposed substantially completely above the at least two isolation features.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mark van Dal, Gerben Doornbos, Georgios Vellianitis, Tsung-Lin Lee, Feng Yuan
  • Publication number: 20170250267
    Abstract: A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure.
    Type: Application
    Filed: May 15, 2017
    Publication date: August 31, 2017
    Inventors: Chia-Chung Chen, Fu-Huan Tsai, Feng Yuan
  • Patent number: 9734790
    Abstract: A method of switching button functions is disclosed. The method is used for switching the functions of buttons used to operate a display when the portable device is connected to the display. The method includes the following steps of: detecting whether the portable device is connected to the display; if yes, determining whether the functions of the buttons can be switched according to whether a button information is received; if yes, pairing each of the buttons with functions provided by the portable device; and storing a pairing information of each of the buttons and the functions provided by the portable device.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: August 15, 2017
    Assignee: WISTRON CORPORATION
    Inventor: Feng-Yuan Chen
  • Patent number: 9721829
    Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Wei-Jen Lai, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh
  • Patent number: 9712461
    Abstract: A data caching method for an Ethernet device is provided. The method includes: receiving data frames from various Ethernet interfaces and converting the Ethernet data frames received from the Ethernet interfaces into data frames having a uniform bit width and a uniform encapsulation format; maintaining a cache address in which data has already been written and a currently idle cache address in a cache; receiving the currently idle cache address and generating a write instruction and/or a read instruction for the cache and performing a write operation and/or a read operation so as to write the data received and processed by an IPC into the currently idle cache or to read data from the cache; and performing bit conversion and format encapsulation on the data that is read according to a read request and outputting the data subjected to the bit conversion and the format encapsulation through a corresponding Ethernet interface. A data caching system for an Ethernet device is also provided.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: July 18, 2017
    Assignee: ZTE CORPORATION
    Inventor: Feng Yuan
  • Patent number: 9711412
    Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Munufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Publication number: 20170160633
    Abstract: A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.
    Type: Application
    Filed: February 17, 2017
    Publication date: June 8, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu LIN, Yi-Jie CHEN, Feng-Yuan CHIU, Ying-Chou CHENG, Kuei-Liang LU, Ya-Hui CHANG, Ru-Gun LIU, Tsai-Sheng GAU
  • Publication number: 20170152638
    Abstract: A snowthrower includes a motor, an auger driven by the motor to rotate, a handle device for a user to operate, an auger housing for containing the auger and a frame for connecting the handle device and the auger housing. The auger housing is made of at least two different materials.
    Type: Application
    Filed: November 29, 2016
    Publication date: June 1, 2017
    Inventors: Xiangqing Fu, Feng Yuan, Keqiong Zhong, Qian Liu, Li Li, Toshinari Yamaoka, Fangjie Nie, Liang Chen
  • Publication number: 20170148917
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Inventors: TSUNG-LIN LEE, CHIH-HAO CHANG, CHIH-HSIN KO, FENG YUAN, JEFF J. XU