Patents by Inventor Feng Yuan

Feng Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9536963
    Abstract: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: January 3, 2017
    Assignee: AU OPTRONICS CORP.
    Inventors: Yu-Min Lin, Kuo-Lung Fang, Feng-Yuan Gan
  • Publication number: 20160364957
    Abstract: A virtual teller machine system, includes an operating room (103) with a display (101) and a console (102) built therein. In the system, a display screen (1011) is alternately attached with a first polarizing film (1011a) having a first polarization direction and a second polarizing film (1011b) having a second polarization direction, a console (102) is provided with a visual device (1021) attached with the first polarizing film (1011a), and in combination with dual-channel video playing control units (1012, 1013, 1014 and 1015), only a user in the operating room (103) can see an operation interface through the visual device (1021), and a user outside the operating room (103) can see other image of a non-operation interface through transparent glass (1031), so as to improve security of user operation and user experience.
    Type: Application
    Filed: July 22, 2015
    Publication date: December 15, 2016
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Feng YUAN, Darong LIANG, Guowei ZHANG, Zhichao LV, Guangdong SHI, Shuai LIU, Jie CHEN
  • Publication number: 20160357270
    Abstract: A method of switching button functions is disclosed. The method is used for switching the functions of buttons used to operate a display when the portable device is connected to the display. The method includes the following steps of: detecting whether the portable device is connected to the display; if yes, determining whether the functions of the buttons can be switched according to whether a button information is received; if yes, pairing each of the buttons with functions provided by the portable device; and storing a pairing information of each of the buttons and the functions provided by the portable device.
    Type: Application
    Filed: October 21, 2015
    Publication date: December 8, 2016
    Inventor: FENG-YUAN CHEN
  • Publication number: 20160358926
    Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Patent number: 9508319
    Abstract: A display and a method for displaying video frames thereof are provided. In the method, a connection state between a first port, a second port and a source device is detected. When only one port is connected to the source device, an original resolution data is provided to the source device through the port and a video streaming transmitted from the source device is received. The video streaming is divided and respectively outputted to the display by a first display controller and a second display controller. When the first port and the second port are both connected to the source device, two adjusted resolution data are provided to the source device through the first port and the second port respectively, and two video streamings transmitted from the source device are received and outputted to the display by the first display controller and the second display controller respectively.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: November 29, 2016
    Assignee: Wistron Corporation
    Inventor: Feng-Yuan Chen
  • Publication number: 20160341202
    Abstract: An electric pump has a pump body, a pump magnet received in the pump body, an impeller received in the pump body and fixed to the pump magnet, and a disc type electric motor. The electric motor includes a stator, disc type coils fixed to a surface of the stator, a rotor rotatably positioned above the coils, and a circuit board electrically connected to the coils. The rotor has a rotor magnet positioned beneath the pump body and magnetically coupled to the pump magnet. When the coils are energized, an axial magnetic field is generated to drive the rotor and, through the magnetic coupling between the rotor magnet and the pump magnet, rotate the impeller.
    Type: Application
    Filed: May 18, 2016
    Publication date: November 24, 2016
    Inventors: Jie CHAI, Ching Hang LEUNG, Kwong Yip POON, Chun Kei YU, Wei Feng YUAN, Tao ZHANG, San Yuan XIAO
  • Publication number: 20160336237
    Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.
    Type: Application
    Filed: July 27, 2016
    Publication date: November 17, 2016
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Hung-Li Chiang, Wei-Jen Lai
  • Patent number: 9484462
    Abstract: An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: November 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng Yuan, Hung-Ming Chen, Tsung-Lin Lee, Chang-Yun Chang, Clement Hsingjen Wann
  • Publication number: 20160315015
    Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.
    Type: Application
    Filed: July 1, 2016
    Publication date: October 27, 2016
    Inventors: Hung-Ming Chen, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh
  • Publication number: 20160247901
    Abstract: The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.
    Type: Application
    Filed: February 12, 2016
    Publication date: August 25, 2016
    Inventors: Feng Yuan, Chih Chieh Yeh, Hung-Li Chiang, Tsung-Lin Lee
  • Patent number: 9425102
    Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Patent number: 9419134
    Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Hung-Li Chiang, Wei-Jen Lai
  • Patent number: 9397097
    Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee Lee, Feng Yuan, Chih Chieh Yeh, Wei-Jen Lai
  • Patent number: 9385046
    Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ming Chen, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh
  • Publication number: 20160186340
    Abstract: An electrolysis apparatus for producing chlorine dioxide, comprising an electrolytic cell for producing chlorine dioxide, a storage tank for receiving the produced chlorine dioxide, and a temperature control system including a coolant supply unit for providing a coolant, a directional valve, a cooling tank and a helical circulation channel. Each cooling tank is configurated to receive the electrolytic cell or the storage tankand is provided with the helical circulation channel surrounding the electrolytic cell or the storage tank. The directional valve is used to switch the flow of the coolant, so as to control the coolant to pass through the helical circulation channel surrounding the storage tank only, or thorugh the helical circulation channels surrounding the storage tank and the electrolytic cell sequentially. Thus, the electrolysis apparatus of the present invention can produce chlorine dioxide with high performance.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 30, 2016
    Inventors: JIUN-HONG TSENG, FENG-YUAN TSENG
  • Patent number: 9374534
    Abstract: A display and a method for displaying multiple frames thereof are provided. In the method, a source device is connected by a video cable. A multiple frame displaying request sent by the source device is received through the video cable. Then, an original resolution of the display is divided into several adjusted resolutions according to the number of frames in the request, and at least one resolution data respectively recording the adjusted resolutions is sent to the source device. At least one video stream sent by the source device is received through the video cable, and frames of the at least one video stream are respectively displayed on at least one corresponding display region of the display.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: June 21, 2016
    Assignee: Wistron Corporation
    Inventor: Feng-Yuan Chen
  • Patent number: 9367655
    Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Chang Shih, Chung-min Fu, Ying-Chou Cheng, Yung-Fong Lu, Feng-Yuan Chiu, Chiu Hsiu Chen
  • Patent number: 9354152
    Abstract: Rheometry apparatus comprises a block of substantially rigid material having an external surface and at least a first internal flow channel, the first internal flow channel being arranged inside the block and substantially in a plane and the block further comprising a plurality of holes, each hole communicating with the first internal flow channel at a respective position along the first internal flow channel and extending from the respective position to said external surface so as to provide access to the first internal flow channel from the external surface, the plurality of holes comprising a first hole communicating with a first said position, for connection to pumping means to drive fluid flow along said first internal flow channel, a second hole communicating with a second position and in which a sensor may be located to measure a property of fluid at the second position, and a third hole communicating with a third position and in which a sensor may be located to measure a property of fluid at the third
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: May 31, 2016
    Assignee: The University of Manchester
    Inventor: Xue-Feng Yuan
  • Publication number: 20160143219
    Abstract: A grass trimmer includes a cutting head for mounting a cutting member, a drive head having a output shaft for driving the cutting head to rotate, and an anti-winding member for preventing the output shaft from being wound to by grass. The drive head includes a drive device to drive the output shaft and a head housing for accommodating the drive device. The output shaft connects to the cutting head and passes through the anti-winding member and the anti-winding member is mounted to the cutting head so as to rotate with the cutting head and is disposed between the cutting head and the head housing so as to fill the space between the cutting head and the head housing.
    Type: Application
    Filed: November 19, 2015
    Publication date: May 26, 2016
    Inventors: Feng Yuan, Ming Peng, Jianpeng Guo, Zichun Tang
  • Publication number: 20160141205
    Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.
    Type: Application
    Filed: January 22, 2016
    Publication date: May 19, 2016
    Inventors: Hung-Li Chiang, Wei-Jen Lai, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh