Patents by Inventor Fenge ZHANG
Fenge ZHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12353373Abstract: Systems and methods described herein relate to the real-time verification of data purges. A first subprocess of a data purging process is executed to purge a plurality of data items. A system accesses purge result data providing an indication of a result of the first subprocess. The system determines, based on the purge result data, that the first subprocess was not executed in accordance with a purge policy associated with the data purging process. In response to determining that the first subprocess was not executed in accordance with the purge policy, the system adjusts a state of the data purging process. A second subprocess of the data purging process is then executed according to the adjusted state.Type: GrantFiled: October 9, 2023Date of Patent: July 8, 2025Assignee: SAP SEInventors: Fen Li, Haipeng Wu, Lei Wang, Yunfeng Jiang, Lai Wei, Feng Zhang
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Patent number: 12350368Abstract: The disclosure includes non-naturally occurring or engineered CRISPR systems and proteins, associated with a delivery system comprising a virus component and a lipid component. The disclosure includes CRISPR proteins associated with capsid proteins, e.g., AAV VP1VP2, and/or VP3, on the surface of or internal to the AAV, along with compositions, systems and complexes involving the AAV-CRISPR protein, nucleic acid molecules and vectors encoding the same, deliver}-systems, and uses therefor.Type: GrantFiled: April 16, 2018Date of Patent: July 8, 2025Assignees: The Broad Institute, Inc., Massachusetts Institute of Technology, Trustees of Tufts CollegeInventors: Feng Zhang, Sourav Choudhury, Qiaobing Xu
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Patent number: 12350398Abstract: The present invention is directed to bioresorbable polymers to be used as bone and tissue adhesives. The present invention is also directed to the synthesis of bioresorbable polymeric molecules bearing adhesive moieties and the use of such compounds in methods to glue and stabilize fractured bones and damaged tissues. The present invention is also directed to the use of such compounds as adhesive sealants for applications in wound care. The present invention is also directed to the use of such compounds as biodegradable ink for applications in tissue engineering and 3D printing. The present invention also relates to the use of such compounds as drug delivery platforms.Type: GrantFiled: April 26, 2023Date of Patent: July 8, 2025Assignee: Evonik Operations GmbHInventors: Teng Xue, Gianluigi Luppi, Natalia Ruggeri Savietto, Howard K. Bowman, III, Paul Joseph Spencer, Andreas Karau, Jian-Feng Zhang, Rosario Lizio, Marshall Scott Jones
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Publication number: 20250215425Abstract: The invention provides for systems, methods, and compositions for targeting nucleic acids. In particular, the invention provides non-naturally occurring or engineered DNA or RNA-targeting systems comprising a novel DNA or RNA-targeting CRISPR effector protein and at least one targeting nucleic acid component like a guide RNA.Type: ApplicationFiled: September 19, 2024Publication date: July 3, 2025Applicants: The Broad Institute, Inc., Massachusetts Institute of Technology, President and Fellows of Harvard CollegeInventors: Feng ZHANG, Bernd Zetsche, Fei RAN, James E. DAHLMAN
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Patent number: 12344838Abstract: The invention provides for systems, methods, and compositions for targeting nucleic acids. In particular, the invention provides non-naturally occurring or engineered DNA-targeting systems comprising a novel DNA-targeting CRISPR effector protein and at least one targeting nucleic acid component like a guide RNA.Type: GrantFiled: February 7, 2022Date of Patent: July 1, 2025Assignees: THE BROAD INSTITUTE, INC., MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Feng Zhang, Bernd Zetsche, Winston Yan, Neville Espi Sanjana, Sara Jones
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Patent number: 12344579Abstract: The invention provides a built-in micro-interface oxidation system for preparing terephthalic acid from p-xylene. The oxidation system includes a first reactor, a rectifying tower and a second reactor which are sequentially connected. A first outlet is disposed on a side wall of the first reactor; a first inlet is disposed on a side wall of the second reactor; a material inlet is disposed on a side wall of the rectifying tower; and a material outlet is disposed at a bottom of the rectifying tower. The first outlet is connected with the material inlet of the rectifying tower; the first inlet is connected with the material outlet of the rectifying tower. Micro-interface units are arranged in the first reactor and the second reactor for dispersing and crushing air into bubbles. Through disposing micro-interface units in reactors, problems of high energy consumption, high raw material consumption and low reaction efficiency are solved.Type: GrantFiled: May 28, 2020Date of Patent: July 1, 2025Assignee: NANJING YANCHANG REACTION TECHNOLOGY RESEARCH INSTITUTE CO., LTD.Inventors: Zhibing Zhang, Zheng Zhou, Feng Zhang, Lei Li, Weimin Meng, Baorong Wang, Gaodong Yang, Huaxun Luo, Guoqiang Yang, Hongzhou Tian, Yu Cao
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Patent number: 12344684Abstract: The invention discloses a micro-interface strengthening reaction system for preparing poly-?-olefin, which includes: a first polymerization reactor and a second polymerization reactor that are connected with each other in sequence, wherein a first micro-interface generator is disposed outside the first polymerization reactor, and a second micro-interface generator is disposed inside the second polymerization reactor. A bottom of the second polymerization reactor is provided with a discharge port, and the discharge port is connected with a hydrogen halide removal tower. By disposing the first micro-interface generator in the first polymerization reactor while disposing the second micro-interface generator in the second polymerization reactor, on the one hand it increases the mass transfer area between the gas phase and the liquid phase material, improves reaction efficiency and reduces energy consumption, and on the other hand it results in a higher evenness of the poly-?-olefin and improved product quality.Type: GrantFiled: June 18, 2020Date of Patent: July 1, 2025Assignee: NANJING YANCHANG REACTION TECHNOLOGY RESEARCH INSTITUTE CO., LTD.Inventors: Zhibing Zhang, Zheng Zhou, Feng Zhang, Lei Li, Weimin Meng, Baorong Wang, Gaodong Yang, Huaxun Luo, Guoqiang Yang, Hongzhou Tian, Yu Cao
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Publication number: 20250212463Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include a metal-all-around contact structure coupled with an S/D region are described herein. In one example, an IC structure may include a region of a doped semiconductor material. An IC structure may include a stack of nanoribbons of a semiconductor material including first portions and second portions on either side of the region, wherein the first portions are in contact with a first side of the region and the second portions are in contact with a second side of the region. An IC structure may include a conductive material over portions of the region between the first side and the second side in a same layer as at least one of the nanoribbons of the stack.Type: ApplicationFiled: December 20, 2023Publication date: June 26, 2025Applicant: Intel CorporationInventors: Robin Chao, Chiao-Ti Huang, Tao Chu, Guowei Xu, Feng Zhang, Ting-Hsiang Hung, Kan Zhang, Yang Zhang, Chia-Ching Lin, Anand S. Murthy
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Publication number: 20250212470Abstract: An IC device may have active regions and one or more isolation regions. The IC device includes gates that are in parallel. One or more semiconductor structures (e.g., fins, nanoribbons, etc.) may extend across each gate in the IC device. Some of the gates are in the active regions. The other gates are in the isolation region. A gate in an active region may be between semiconductor regions, which may function as the source region and drain region of a transistor. A gate in an isolation region may be between insulator regions. The insulator regions may be formed from the backside of the IC device. For instance, semiconductor regions may be formed in both the active regions and the isolation regions. The semiconductor regions in the regions designated to be isolation regions may be removed from the backside and filled with one or more electrical insulators.Type: ApplicationFiled: December 20, 2023Publication date: June 26, 2025Applicant: Intel CorporationInventors: Feng Zhang, Tao Chu, Guowei Xu, Kan Zhang, Chiao-Ti Huang, Minwoo Jang, Yanbin Luo, Ting-Hsiang Hung, Robin Chao, Chia-Ching Lin, Yang Zhang, Anand S. Murthy
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Publication number: 20250203975Abstract: An IC device may have activation regions and an isolation region between the active regions. An active region may include one or more transistors. The IC device includes gates that are in parallel. Some of the gates are in the active regions. The other gates are in the isolation region. A source or drain region may be formed between a gate in the isolation region and a gate in a transistor in the first direction. The IC device may include one or more semiconductor structures that extend across a gate in a transistor, and the semiconductor structures may constitute a channel region of the transistor. The IC device may also include one or more semiconductor structures that extend across an individual gate in the isolation region. An insulative structure may be formed between two gates in the isolation region. The insulative structure may be over the source or drain region.Type: ApplicationFiled: December 14, 2023Publication date: June 19, 2025Inventors: Guowei Xu, Paul Packan, Anand S. Murthy, Chia-Ching Lin, Yanbin Luo, Minwoo Jang, Yang Zhang, Chung-Hsun Lin, Tao Chu, Ting-Hsiang Hung, Chiao-Ti Huang, Feng Zhang, Robin Chao, Kan Zhang
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Publication number: 20250204000Abstract: An IC device may include a support structure and a transistor built based on the support structure. The transistor may include an electrical contact over a semiconductor region in the transistor. The electrical contact may be a single structure formed by filling a single opening region with a conductive material. In an example, an end of the electrical contact may contact the semiconductor region, and another end of the electrical contact may contact a deep via. The deep via may extend through the support structure and contact a backside metal layer for delivering power or signal to the semiconductor region. In another example, an end of the electrical contact may contact the semiconductor region, and another end of the electrical contact may contact a semiconductor region in another transistor. A dielectric structure may be between the two semiconductor regions.Type: ApplicationFiled: December 15, 2023Publication date: June 19, 2025Applicant: Intel CorporationInventors: Kan Zhang, Chiao-Ti Huang, Guowei Xu, Saurabh Acharya, Shengsi Liu, Leonard P. Guler, Yang Zhang, Tao Chu, Robin Chao, Ting-Hsiang Hung, Feng Zhang, Chia-Ching Lin, Anand S. Murthy
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Publication number: 20250204154Abstract: The present application relates to an array base plate, a display panel, and a method for manufacturing an array base plate, and the array base plate includes: a substrate; a device layer stacked on a side of the substrate along a thickness direction thereof, wherein the device layer includes a first type transistor, a second type transistor, and a capacitor, the first type transistor includes a first source-drain electrode, the second type transistor includes a second source-drain electrode, and the capacitor includes a first electrode plate and a second electrode plate; wherein the first electrode plate is provided on the same layer as at least one of the first source-drain electrode and the second source-drain electrode, and the second electrode plate is provided on a side of the first type transistor and the second type transistor away from the substrate along the thickness direction.Type: ApplicationFiled: February 28, 2025Publication date: June 19, 2025Applicants: Hefei Visionox Technology Co., Ltd., KunShan Go-Visionox Opto-Electronics Co., Ltd.Inventors: Jie WANG, Zhancheng MIAO, Dandan SUN, Zhe DU, Qing BAI, Yafei SUN, Jianjun LU, Feng ZHANG, Junfeng LI
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Patent number: 12332351Abstract: The embodiments of this application disclose a time of flight measurement method, including: performing delay processing on an echo signal to obtain N delayed signals; generating X clock signals with different phases based on a multi-phase clock unit; performing delay latch on the N delayed signals based on each of the X clock signals; determining a to-be-processed time of flight based on the reference signal and each of the delay latch result; and determining a target time of flight based on the X to-be-processed time of flights, where the target time of flight is a time difference between emitting the reference signal and receiving the echo signal. With the embodiment of this application, the precision of measuring the time of flight of the echo signal can be effectively improved while saving costs and simplifying calculations.Type: GrantFiled: January 9, 2024Date of Patent: June 17, 2025Assignee: Suteng Innovation Technology Co., Ltd.Inventor: Feng Zhang
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Patent number: 12329744Abstract: Compositions and methods of preparing amorphous drug formulations through hot melt extrusion which result in decreased decomposition of the desired drug are provided herein. Also provided are methods and compositions which further comprise a pharmaceutically acceptable thermoplastic polymer. In some embodiments, these compositions comprise a therapeutically active agent which is only sparingly soluble in water.Type: GrantFiled: January 29, 2021Date of Patent: June 17, 2025Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: Feng Zhang, Abbe Miller, Siyuan Huang, Robert O. Williams, III
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Publication number: 20250194179Abstract: Fabrication methods for integrated circuit (IC) structures and devices including asymmetric source and drain regions are described herein. In one example, an integrated circuit structure includes a transistor including a first region and a second region, where one of the first region and the second region is a source region of the transistor, and another of the first region and the second region is a drain region of the transistor, and where the first and second regions have different widths. In one example, the first region has a first width and the second region has a second width that is smaller than the first width.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Tao Chu, Guowei Xu, Chiao-Ti Huang, Robin Chao, Feng Zhang, Ting-Hsiang Hung, Chia-Ching Lin, Yang Zhang, Kan Zhang, Nick Lindert, Marvin Young Paik, Paul Packan, Chung-Hsun Lin, Anand S. Murthy, Minwoo Jang
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Publication number: 20250194211Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include a conductive via with front-side and back-side connections with an S/D region are described herein. In one example, an IC structure includes a conductive via extending between a first layer and a second layer and an S/D region of a transistor between the first layer and the second layer, where the S/D region includes a first semiconductor material and a second semiconductor material. In one such example, the second semiconductor material may be epitaxially grown on the first semiconductor material of the S/D region from a back side of the IC structure. Conductive elements in layers over and under the conductive via may couple the conductive via with the S/D region from both the front-side and back-side S/D contact structures.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Applicant: Intel CorporationInventors: Ting-Hsiang Hung, Yang Zhang, Robin Chao, Guowei Xu, Tao Chu, Chiao-Ti Huang, Feng Zhang, Chia-Ching Lin, Kan Zhang, Anand S. Murthy
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Publication number: 20250179453Abstract: Disclosed and claimed are mutation(s) or modification(s) of the CRISPR enzyme, for example a Cas enzyme such as a Cas9, which obtain an improvement, for instance a reduction, as to off-target effects of a CRISPR-Cas or CRISPR-enzyme or CRISPR-Cas9 system or complex containing or including such a mutated or modified Cas or CRISPR enzyme or Cas9. Methods for making and using and uses of such mutated or modified Cas or CRISPR enzyme or Cas9 and systems or complexes containing the same and products from such methods and uses are also disclosed and claimed.Type: ApplicationFiled: October 3, 2024Publication date: June 5, 2025Applicants: The Broad Institute, Inc., Massachusetts Institute of TechnologyInventors: Feng ZHANG, Linyi GAO, Bernd ZETSCHE, Ian SLAYMAKER
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Publication number: 20250176758Abstract: An air outlet apparatus for use in an air fryer includes a first outlet portion connected to a cold air duct for discharging cold air, a second outlet portion below the first outlet portion and connected to a hot air duct for discharging hot air, a first baffle portion opposite to the first outlet portion, an extension portion between the first outlet portion and the first baffle portion, and a mixing chamber for mixing the cold air and hot air. The mixing chamber is surrounded partially by a plane where the first outlet portion is located, the first baffle portion, and the extension portion.Type: ApplicationFiled: November 30, 2023Publication date: June 5, 2025Inventors: Min LIN, Lei LIU, Zhibin CHENG, Xiangyu YIN, Feng ZHANG
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Publication number: 20250180956Abstract: A display panel includes an array substrate. The array substrate includes: a first flexible substrate; a planarization layer disposed on the first flexible substrate and provided with a groove; a source-drain electrode portion disposed in the groove, a surface of the source-drain electrode portion away from the first flexible substrate being flush with a surface of the planarization layer; an organic semiconductor portion disposed on a side of the source-drain electrode portion and the planarization layer away from the first flexible substrate; a gate insulating portion disposed on a side of the organic semiconductor portion away from the first flexible substrate; and a first gate disposed on a side of the gate insulating portion away from the first flexible substrate.Type: ApplicationFiled: February 12, 2025Publication date: June 5, 2025Applicant: BOE Technology Group Co., Ltd.Inventors: Liwen DONG, Changhan HSIEH, Dongfei HOU, Feng ZHANG, Zhao CUI, Detian MENG, Zhijun LV, Wenqu LIU, Yuqiao LI
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Patent number: 12321466Abstract: Techniques for hierarchical encryption for data storage are disclosed, in one or more embodiments. These techniques include parsing an electronic database storage request, based on the syntax of the request, to identify a plurality of request elements and determining, using one or more trained machine learning (ML) models, one or more sensitivities associated with the plurality of request elements. The techniques further include identifying one or more encryption techniques for the plurality of request elements based on the one or more sensitivities, encrypting data associated with the database storage request using the identified one or more encryption techniques, and storing the encrypted data and one or more associated encryption keys in an electronic database, using the electronic database storage request.Type: GrantFiled: January 11, 2022Date of Patent: June 3, 2025Assignee: International Business Machines CorporationInventors: Zhe Hua Peng, Peng Hui Jiang, Ting Yin, Jun Su, Feng Zhang