Abstract: Provided is a display substrate. The display substrate includes: a substrate body; and a plurality of support pillars disposed on the substrate body, wherein the support pillar includes a first surface in contact with the substrate body, and a second surface opposite to the first surface; wherein in any direction parallel to the substrate body, a ratio of a width of the first surface to a width of the second surface is greater than or equal to 0.8, and is less than or equal to 1.2.

Abstract: Technologies directed to respiration monitoring based on noise channel state information (CSI) data are described. A method includes receiving CSI data representing channel properties of a wireless channel used by a first wireless device and a second wireless device located in a geographical region. The method generates a set of CSI samples by sampling the CSI data and removes one or more outlier CSI samples using a sparse outlier process, and removes a cluster of outlier samples using a cluster outlier process. The method determines Fast Fourier Transform (FFT) data for each channel subcarrier index and a signal-to-noise ratio (SNR) value for each channel subcarrier index, and identifies a first number of channel subcarrier indexes having highest SNR values to obtain a subset of FFT data, which represents a breathing spectrum. The method determines a respiratory rate of a user in the geographical region from the subset of the FFT data.

Abstract: Systems and methods described herein relate to the real-time verification of data purges. A first subprocess of a data purging process is executed to purge a plurality of data items. A system accesses purge result data providing an indication of a result of the first subprocess. The system determines, based on the purge result data, that the first subprocess was not executed in accordance with a purge policy associated with the data purging process. In response to determining that the first subprocess was not executed in accordance with the purge policy, the system adjusts a state of the data purging process. A second subprocess of the data purging process is then executed according to the adjusted state.

Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.

Abstract: Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.

Abstract: The present disclosure provides a method for manufacturing an aspherical prism and an aspherical prism. The method includes step S1, forming a prism and a lens into one piece to obtain a forming body glass by using a hot-pressing molding; step S2, adhering the forming body glass to a tooling, and performing a right-angle surface milling on the forming body glass according to a preset size while reserving a processing amount for a polishing process; step S3, adhering the forming body glass formed after the right-angle surface milling to an optical backing plate for polishing; step S4, cutting the forming body glass formed after the polishing; step S5, coating the forming body glass formed after the cutting; and step S6, inking the forming body glass formed after the coating. The method can improve the structural precision and processing efficiency of the aspherical prism.

Abstract: Trench contact structures with etch stop layers, and methods of fabricating trench contact structures with etch-stop layers, are described. In an example, an integrated circuit structure includes a fin structure. An epitaxial source or drain structure is on the fin structure. An isolation structure is laterally adjacent to sides of the fin structure. A dielectric layer is on at least a portion of a top surface of the isolation structure and partially surrounds the epitaxial source or drain structure and leaves an exposed portion of the epitaxial source or drain structure. A conductive trench contact structure is on the exposed portion of the epitaxial source or drain structure. The conductive trench contact structure does not extend into the isolation structure.

Abstract: Disclosed in the present invention is a non-oriented electrical steel plate with good magnetic performance. The non-oriented electrical steel plate contains Fe and inevitable impurities, and further contains the following chemical elements, in percentage by mass: 0<C?0.0015%, Si: 0.2-1.8%, Mn: 0.2-0.4%, Al: 0.2-0.6%, V: 0.002-0.005%, and N<0.002%. In addition, further disclosed in the present invention is a manufacturing method for the non-oriented electrical steel plate with good magnetic performance. The manufacturing method comprises the steps of: (1) smelting and casting: (2) hot rolling, wherein a steel coil obtained after the hot rolling is directly introduced to the next step without being subjected to normalizing annealing or cover annealing; (3) acid pickling; (4) cold rolling; and (5) continuous annealing, wherein the steel plate is heated to a target soaking temperature at a heating rate of 50-5000° C./s after the cold rolling.

Abstract: Multiple voltage threshold integrated circuit structures with local layout effect tuning, and methods of fabricating multiple voltage threshold integrated circuit structures with local layout effect tuning, are described. For example, an integrated circuit structure includes a first fin structure or vertical arrangement of horizontal nanowires. A second fin structure or vertical arrangement of horizontal nanowires is laterally spaced apart from the first fin structure or vertical arrangement of horizontal nanowires. An N-type gate structure is over the first fin structure or vertical arrangement of horizontal nanowires. A P-type gate structure is over the second fin structure or vertical arrangement of horizontal nanowires, the P-type gate structure in contact with the N-type gate structure with a PN boundary between the P-type gate structure and the N-type gate structure.

Abstract: Described herein are methods and uses thereof for in vivo evaluating functions of multiple genes in parallel by combining in utero genetic perturbation of progenitor cells and single-cell transcriptomic profiling of progeny cells in animals. These methods can be used, among other things, to reveal in vivo gene functions in a cell type-specific manner.

Abstract: A cerium-zirconium-aluminum-based composite material, a cGPF catalyst and a preparation method thereof are provided. The cerium-zirconium-aluminum-based composite material adopts a stepwise precipitation method, firstly preparing an aluminum-based pre-treated material, then coprecipitating the aluminum-based pre-treated material with zirconium and cerium sol, and finally roasting at high temperature to obtain the cerium-zirconium-aluminum-based composite material. The cerium-zirconium-aluminum-based composite material has better compactness and higher density, and when it is used in cGPF catalyst, it occupies a smaller volume of pores on the catalyst carrier, such that cGPF catalyst has lower back pressure and better ash accumulation resistance, which is beneficial to large-scale application of cGPF catalyst.

Abstract: The invention provides for systems, methods, and compositions for targeting nucleic acids. In particular, the invention provides non-naturally occurring or engineered DNA-targeting systems comprising a novel DNA-targeting CRISPR effector protein and at least one targeting nucleic acid component like a guide RNA. Methods for making and using and uses of such systems, methods, and compositions and products from such methods and uses are also disclosed and claimed.

Abstract: The present disclosure relates to the field of display technology, and provides an optical module, a manufacturing method thereof, and a display device. The optical module includes: a substrate; a black matrix arranged on the substrate and a plurality of optical lenses spaced apart from each other, wherein an orthogonal projection of a gap between adjacent optical lenses onto the substrate is located within an orthogonal projection of the black matrix onto the substrate, and the black matrix is made of a ferrous metal oxide.

Abstract: Systems and methods described herein relate to the efficient handling of data purge requests in the context of a distributed storage system. A plurality of data purge requests is stored in a first data structure. The data purge requests may be grouped into batches that are processed at least partially in parallel. A first data purge request from the plurality of data purge requests is successfully processed, and is moved from the first data structure to a second data structure. Processing of a second data purge request from the plurality of data purge requests is unsuccessful. The second data purge request is retained in the first data structure. Purge status data is generated based on the first data purge request being in the second data structure and the second data purge request being in the first data structure. The purge status data may be presented at a user device.

Abstract: The present disclosure provides for systems, methods, and compositions for targeting nucleic acids. In particular, the invention provides mutated Cas13 proteins and their use in modifying target sequences as well as mutated Cas13 nucleic acid sequences and vectors encoding mutated Cas13 proteins and vector systems or CRISPR-Cas13 systems.

Abstract: Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction. Airgaps are provided in the regions between the gate structures and the adjacent source/drain contacts. The airgaps have a low dielectric constant (e.g., around 1.0) to reduce the parasitic capacitance between the conductive structures.

Abstract: The invention provides for delivery, engineering and optimization of systems, methods, and compositions for manipulation of sequences and/or activities of target sequences. Provided are delivery systems and tissues of organ which are targeted as sites for delivery. Also provided are vectors and vector systems some of which encode one or more components of a CRISPR complex, as well as methods for the design and use of such vectors. Also provide dare methods of directing CRISPR complex formation in eukaryotic cells to ensure enhanced specificity for target recognition and avoidance of toxicity and to edit or modify a target site in a genomic locus of interest to alter or improve the status of a disease or a condition.

Abstract: The present disclosure discloses a speaker comprising a frame, a vibration system, a magnetic circuit system, and a flexible circuit board embedded in the bottom end of the frame; the vibration system and the magnetic circuit system are respectively fixed at both ends of the frame and collectively enclosed into a sound producing cavity; the magnetic circuit system comprising a lower clamping plate and a main magnet; the lower clamping plate comprising a lower clamping body, two rectangular through-holes and two first flanges; each first flange having a shape and size matching the corresponding rectangular through-hole; each of two first flaps spaced from the main magnet and forming the magnetic gap collectively; the speaker further comprising two breathable isolators fixed to the lower clamping body and covering each of the rectangular through-holes. FPC alignment installation is convenient, cost savings; the acoustic performance of the speaker is good.

Abstract: Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.

Abstract: Integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. For example, an integrated circuit structure includes an NMOS region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. The integrated circuit structure also includes a PMOS region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. A gate line is shared between the NMOS region and the PMOS region, and a trench contact structure is shared between the NMOS region and the PMOS region.