Patents by Inventor Feras Eid

Feras Eid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10845380
    Abstract: Embodiments of the invention include a microelectronic device having a sensing device and methods of forming the sensing device. In an embodiment, the sensing device includes a mass and a plurality of beams to suspend the mass. Each beam comprises first and second conductive layers and an insulating layer positioned between the first and second conductive layers to electrically isolate the first and second conductive layers. The first conductive layer is associated with drive signals and the second conductive layer is associated with sense signals of the sensing device.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Feras Eid, Henning Braunisch, Georgios C. Dogiamis, Sasha N. Oster
  • Patent number: 10840430
    Abstract: Embodiments of the invention include a sensing device that includes a base structure having a proof mass that is positioned in proximity to a cavity of an organic substrate, a piezoelectric material in contact with a first electrode of the base structure, and a second electrode in contact with the piezoelectric material. The proof mass deflects in response to application of an external force or acceleration and this deflection causes a stress in the piezoelectric material which generates a voltage differential between the first and second electrodes.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Feras Eid, Sasha N. Oster, Georgios C. Dogiamis, Shawna M. Liff, Adel A. Elsherbini, Thomas L. Sounart, Johanna M. Swan
  • Patent number: 10816733
    Abstract: Embodiments of the invention include an optical routing device that includes an organic substrate. According to an embodiment, an array of cavities are formed into the organic substrate and an array of piezoelectrically actuated mirrors may be anchored to the organic substrate with each piezoelectrically actuated mirror extending over a cavity. In order to properly rout incoming optical signals, the optical routing device may also include a routing die mounted on the organic substrate. The routing die may be electrically coupled to each of the piezoelectrically actuated mirrors and is able to generated a voltage across the first and second electrodes of each piezoelectrically actuated mirror. Additionally, a photodetector may be electrically coupled to the routing die. According to an embodiment, an array of fiber optic cables may be optically coupled with one of the piezoelectrically actuated mirrors and optically coupled with the photodetector.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Sasha N. Oster, Johanna M. Swan, Feras Eid, Thomas L. Sounart, Aleksandar Aleksov, Shawna M. Liff, Baris Bicen, Valluri R. Rao
  • Patent number: 10811366
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Publication number: 20200312796
    Abstract: An inductor in a device package and a method of forming the inductor in the device package are described. The inductor includes a first conductive layer disposed on a substrate. The inductor also has one or more hybrid magnetic additively manufactured (HMAM) layers disposed over and around the first conductive layer to form one or more via openings over the first conductive layer. The inductor further includes one or more vias disposed into the one or more via openings, wherein the one or more vias are only disposed on the portions of the exposed first conductive layer. The inductor has a dielectric layer disposed over and around the one or more vias, the HMAM layers, and the substrate. The inductor also has a second conductive layer disposed over the one or more vias and the dielectric layer.
    Type: Application
    Filed: September 30, 2017
    Publication date: October 1, 2020
    Inventors: Henning BRAUNISCH, Feras EID, Georgios C. DOGIAMIS
  • Publication number: 20200312782
    Abstract: A device package and a method of forming the device package are described. The device package includes a substrate having a ground plane and dies disposed on the substrate. The dies are electrically coupled to the substrate with solder balls or bumps surrounded by an underfill layer. The device package has a mold layer disposed over and around the dies, the underfill layer, and the substrate. The device package further includes an additively manufactured electromagnetic interference (EMI) shield layer disposed on an outer surface of the mold layer. The additively manufactured EMI shield layer is electrically coupled to the ground plane of the substrate. The outer surface of the mold layer may include a topmost surface and one or more sidewalls that are covered with the additively manufactured EMI shield layer. The additively manufactured EMI shield may include a first and second additively manufactured EMI shield layers and an additively manufactured EMI shield frame.
    Type: Application
    Filed: September 30, 2017
    Publication date: October 1, 2020
    Inventors: Feras EID, Henning BRAUNISCH, Shawna M. LIFF, Georgios C. DOGIAMIS, Johanna M. SWAN
  • Publication number: 20200287520
    Abstract: Hybrid filters and more particularly filters having acoustic wave resonators (AWRs) and lumped component (LC) resonators and packages therefor are described. In an example, a packaged filter includes a package substrate, the package substrate having a first side and a second side, the second side opposite the first side. A first acoustic wave resonator (AWR) device is coupled to the package substrate, the first AWR device comprising a resonator. A plurality of inductors is in the package substrate.
    Type: Application
    Filed: December 28, 2017
    Publication date: September 10, 2020
    Inventors: Telesphor KAMGAING, Feras EID, Georgios C. DOGIAMIS, Vijay K. NAIR, Johanna M. SWAN
  • Publication number: 20200259478
    Abstract: Embodiments of the invention include an acoustic wave resonator (AWR) module. In an embodiment, the AWR module may include a first AWR substrate and a second AWR substrate affixed to the first AWR substrate. In an embodiment, the first AWR substrate and the second AWR substrate define a hermetically sealed cavity. A first AWR device may be positioned in the cavity and formed on the first AWR substrate, and a second AWR device may be positioned in the cavity and formed on the second AWR substrate. In an embodiment, a center frequency of the first AWR device is different than a center frequency of the second AWR device. In additional embodiment of the invention, the AWR module may be integrated into a hybrid filter. The hybrid filter may include an AWR module and other RF passive devices embedded in a packaging substrate.
    Type: Application
    Filed: December 28, 2017
    Publication date: August 13, 2020
    Inventors: Georgios C. DOGIAMIS, Telesphor KAMGAING, Feras EID, Vijay K. NAIR, Johanna M. SWAN
  • Publication number: 20200235716
    Abstract: Packaged RF front end systems including a hybrid filter and an active circuit in a single package are described. In an example, a package includes an active die comprising an acoustic wave resonator. A package substrate is electrically coupled to the active die. A seal frame surrounds the acoustic wave resonator and is attached to the active die and to the package substrate, the seal frame hermetically sealing the acoustic wave resonator in a cavity between the active die and the package substrate.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 23, 2020
    Inventors: Feras EID, Telesphor KAMGAING, Georgios C. DOGIAMIS, Vijay K. NAIR, Johanna M. SWAN
  • Publication number: 20200235449
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 23, 2020
    Inventors: Adel A. ELSHERBINI, Mathew MANUSHAROW, Krishna BHARATH, Zhichao ZHANG, Yidnekachew S. MEKONNEN, Aleksandar ALEKSOV, Henning BRAUNISCH, Feras EID, Javier SOTO
  • Publication number: 20200235082
    Abstract: A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.
    Type: Application
    Filed: September 30, 2017
    Publication date: July 23, 2020
    Inventors: Feras EID, Johanna M. SWAN, Shawna M. LIFF
  • Patent number: 10721568
    Abstract: Embodiments of the invention include an acoustic transducer device having a base structure that is positioned in proximity to a cavity of an organic substrate, a piezoelectric material in contact with a first electrode of the base structure, and a second electrode in contact with the piezoelectric material. In one example, for a transmit mode, a voltage signal is applied between the first and second electrodes and this causes a stress in the piezoelectric material which causes a stack that is formed with the first electrode, the piezoelectric material, and the second electrode to vibrate and hence the base structure to vibrate and generate acoustic waves.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Georgios C. Dogiamis, Feras Eid, Adel A. Elsherbini, Johanna Swan, Shawna M. Liff, Thomas L. Sounart, Sasha N. Oster
  • Publication number: 20200227336
    Abstract: A device package and a method of forming a device package are described. The device package includes a lid with one or more legs on an outer periphery of the lid, a top surface, and a bottom surface, where the lid is disposed on the substrate. The legs of the lid are attached to the substrate with a sealant. The device package also has one or more dies disposed on the substrate. The die(s) are below the bottom surface of the lid, where each of the dies has a top surface and a bottom surface. The device package further includes a retaining structure disposed between the bottom surface of the lid and the top surface of the die, where the retaining structure has one or more inner walls. The device package includes a thermal interface material disposed within the inner walls of the retaining structure and above the top surface of the die.
    Type: Application
    Filed: September 30, 2017
    Publication date: July 16, 2020
    Inventor: Feras EID
  • Publication number: 20200227335
    Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.
    Type: Application
    Filed: September 30, 2017
    Publication date: July 16, 2020
    Inventors: Feras EID, Johanna M. SWAN, Sergio CHAN ARGUEDAS, John J. BEATTY
  • Publication number: 20200219861
    Abstract: RF front end systems or modules with an acoustic wave resonator (AWR) on an interposer substrate are described. In an example, an integrated system includes an active die, the active die comprising a semiconductor substrate having a plurality of active circuits therein. An interposer is also included, the interposer comprising an acoustic wave resonator (AWR). A seal frame couples the active die to the interposer, the seal frame surrounding the acoustic wave resonator and hermetically sealing the acoustic wave resonator between the active die and the interposer.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 9, 2020
    Inventors: Telesphor KAMGAING, Vijay K. NAIR, Feras EID, Georgios C. DOGIAMIS, Johanna M. SWAN, Stephan LEUSCHNER
  • Publication number: 20200203298
    Abstract: An apparatus is provided which comprises: a first set of one or more metal pads on a first substrate surface, the first set of one or more metal pads to couple with contacts of an integrated circuit die, a second set of one or more metal pads on the first substrate surface, the second set of one or more metal pads to couple with semiconductor surfaces of the integrated circuit die, one or more thermal regions below the first substrate surface, wherein the one or more thermal regions comprise thermally conductive material and are coupled with the second set of one or more metal pads, dielectric material adjacent the one or more thermal regions, and one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts coupled with the first set of one or more metal pads, and the one or more conductive contacts to couple with contacts of a printed circuit board. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: June 25, 2020
    Applicant: INTEL CORPORATION
    Inventors: Feras Eid, Johanna Swan
  • Publication number: 20200194335
    Abstract: A device package and a method of forming a device package are described. The device package includes a plurality of posts disposed on a substrate. Each post has a top surface and a bottom surface that is opposite from the top surface. The device package also has one or more dies disposed on the substrate. The dies are adjacent to the plurality of posts on the substrate. The device package further includes a lid disposed above the plurality of posts and the one or more dies on the substrate. The lid has a top surface and a bottom surface that is opposite from the top surface. Lastly, an adhesive layer attaches the top surfaces of the plurality of posts and the bottom surface of the lid. The device package may also include one or more thermal interface materials (TIMs) disposed on the dies.
    Type: Application
    Filed: September 30, 2017
    Publication date: June 18, 2020
    Inventors: Feras EID, Dinesh PADMANABHAN RAMALEKSHMI THANU, Sergio CHAN ARGUEDAS, Johanna M. SWAN, John J. BEATTY
  • Publication number: 20200176352
    Abstract: An integrated circuit die includes a device side and a backside opposite the device side, wherein the backside includes a heat transfer enhancement configuration formed therein or a heat transfer enhancement structure formed thereon each of which enhance a heat transfer area or a boiling nucleation site density over a planar backside surface. A method of forming an integrated circuit assembly includes disposing a heat exchanger on a multi-chip package, the multi-chip package including at least one integrated circuit die including a device side and an opposite backside includes a heat transfer enhancement configuration formed therein or a heat enhancement structure formed thereon; and contacting the backside of the at least one integrated circuit die with water or other cooling fluids, such as a mixture of water and antifreeze, alcohol, inert fluorinated hydrocarbon, helium, and/or other suitable cooling fluid (either liquid or gas).
    Type: Application
    Filed: June 30, 2017
    Publication date: June 4, 2020
    Inventors: Je-Young CHANG, Chandra M. JHA, Shankar DEVASENATHIPATHY, Feras EID, John C. JOHNSON
  • Publication number: 20200168402
    Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a piezoelectrically actuated tunable capacitor having a variable capacitance formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers. A piezoelectric actuator of the tunable capacitor includes first and second conductive electrodes and a piezoelectric layer that is positioned between the first and second conductive electrodes.
    Type: Application
    Filed: June 27, 2017
    Publication date: May 28, 2020
    Inventors: Feras EID, Aleksandar ALEKSOV, Georgios C. DOGIAMIS, Thomas L. SOUNART, Johanna M. SWAN
  • Patent number: 10658566
    Abstract: Embodiments of the invention include piezoelectrically driven switches that are used for modifying a background color or light source color in display systems, and methods of forming such devices. In an embodiment, a piezoelectrically actuated switch for modulating a background color in a display may include a photonic crystal that has a plurality of blinds oriented substantially perpendicular to a surface of the display. In an embodiment, the blinds include a black surface and a white surface. The switch may also include an anchor spaced away from an edge of the photonic crystal and a piezoelectric actuator formed on the surface of the anchor and a surface of the photonic crystal. Some embodiments may include a photonic crystal that is a multi-layer polymeric structure or a polymer chain with a plurality of nanoparticles spaced at regular intervals on the polymer chain.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Feras Eid, Aleksandar Aleksov, Sasha N. Oster, Baris Bicen, Thomas L. Sounart, Johanna M. Swan, Adel A. Elsherbini, Valluri R. Rao