Patents by Inventor Feras Eid

Feras Eid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wearable sensing patch technologies
    Patent number: 10959633
    Abstract: Sensing patch systems are disclosed herein. A sensing patch system includes a flexible substrate and a sensor node. The flexible substrate includes one or more substrate sensors configured to provide sensor data, one or more substrate conductors electrically coupled to a corresponding substrate sensor to conduct the sensor data provided by the corresponding substrate sensor, and a node interface. The sensor node includes a substrate interface configured to receive the node interface of the flexible substrate. The sensor node is configured to receive the sensor data provided by the substrate sensors, process the sensor data, and communicate the processed sensor data to a remote device.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Amit Baxi, Adel Elsherbini, Vincent Mageshkumar, Sasha Oster, Aleksandar Aleksov, Feras Eid
  • DUAL-SUBSTRATE WAVEGUIDE FILTER
    Publication number: 20210091443
    Abstract: Embodiments may relate to an assembly that includes a first package substrate with a first electromagnetic cavity. The assembly may further include a second package substrate with a second electromagnetic cavity that is adjacent to the first electromagnetic cavity. The first and second electromagnetic cavities may form a millimeter wave (mmWave) resonant cavity of a mmWave filter. Other embodiments may be described or claimed.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Telesphor Kamgaing, Georgios Dogiamis, Feras Eid, Johanna M. Swan
  • Radio frequency (RF) module with shared inductor
    Patent number: 10951248
    Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM) with a first filter and a second filter. The RF FEM may include a termination inductor coupled to ground, and a switch that is to selectively couple the first filter and the second filter to the termination inductor. Other embodiments may be described or claimed.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Feras Eid, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
  • CAPACITOR-WIREBOND PAD STRUCTURES FOR INTEGRATED CIRCUIT PACKAGES
    Publication number: 20210066184
    Abstract: Disclosed herein are capacitor-wirebond pad structures for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die and an IC package support. The IC package support may include a capacitor, and the capacitor may include a first capacitor plate, a second capacitor plate, and a capacitor dielectric between the first capacitor plate and the second capacitor plate. The die may be wirebonded to the first capacitor plate.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Applicant: INTEL CORPORATION
    Inventors: Aleksandar Aleksov, Feras Eid, Georgios Dogiamis, Telesphor Kamgaing, Johanna M. Swan
  • TUNABLE CAPACITOR ARRANGEMENTS IN INTEGRATED CIRCUIT PACKAGE SUBSTRATES
    Publication number: 20210066265
    Abstract: Disclosed herein are tunable capacitor arrangements in integrated circuit (IC) package substrates, as well as related methods and devices. For example, in some embodiments, an IC package substrate may include a first embedded capacitor, a second embedded capacitor, and a fuse electrically coupled between the first embedded capacitor and the second embedded capacitor such that when the fuse is in a closed state, the first embedded capacitor and the second embedded capacitor are connected in parallel, and when the fuse is in an open state, the first embedded capacitor and the second embedded capacitor are not connected in parallel.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Aleksandar Aleksov, Telesphor Kamgaing, Georgios Dogiamis, Johanna M. Swan, Sivakumar Nagarajan, Nitin A. Deshpande, Omkar G. Karhade, William James Lambert
  • MONOLITHIC DIE WITH ACOUSTIC WAVE RESONATORS AND ACTIVE CIRCUITRY
    Publication number: 20210067132
    Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM). The RF FEM may include an integrated die with an active portion and an acoustic wave resonator (AWR) portion adjacent to the active portion. The RF FEM may further include a lid coupled with the die. The lid may at least partially overlap the AWR portion at a surface of the die. Other embodiments may be described or claimed.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Applicant: Intel Corporation
    Inventors: Telesphor Kamgaing, Georgios Dogiamis, Feras Eid, Aleksandar Aleksov, Johanna M. Swan
  • Microelectronic devices designed with ultra-high-k dielectric capacitors integrated with package substrates
    Patent number: 10937594
    Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a capacitor formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers. The capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Thomas L. Sounart, Aleksandar Aleksov, Feras Eid, Georgios C. Dogiamis, Johanna M. Swan, Kristof Darmawikarta
  • WARPAGE MITIGATION STRUCTURES CREATED ON SUBSTRATE USING HIGH THROUGHPUT ADDITIVE MANUFACTURING
    Publication number: 20210057354
    Abstract: Device package and method of forming a device package are described. The device package has a substrate with dies disposed on the substrate. Each die has a bottom surface that is electrically coupled to the substrate and a top surface. The device package further includes a plurality of stiffeners disposed directly on the substrate. The stiffeners may be directly attached to a top surface of the substrate without an adhesive layer. The device package may include stiffeners with one or more different sizes and shapes, including at least one of a rectangular stiffener, a picture frame stiffener, a L-shaped stiffener, a H-shaped stiffener, and a round pillar stiffener. The device package may have the stiffeners disposed on the top surface of the substrate using a cold spray process. The device package may also include a mold layer formed around and over the dies, the stiffeners, and the substrate.
    Type: Application
    Filed: September 30, 2017
    Publication date: February 25, 2021
    Inventor: Feras EID
  • Piezoelectric package-integrated current sensing devices
    Patent number: 10921349
    Abstract: Embodiments of the invention include a current sensing device for sensing current in an organic substrate. The current sensing device includes a released base structure that is positioned in proximity to a cavity of the organic substrate and a piezoelectric film stack that is positioned in proximity to the released base structure. The piezoelectric film stack includes a piezoelectric material in contact with first and second electrodes. A magnetic field is applied to the current sensing device and this causes movement of the released base structure and the piezoelectric stack which induces a voltage (potential difference) between the first and second electrodes.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Georgios C. Dogiamis, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Jelena Culic-Viskota, Thomas L. Sounart, Feras Eid, Sasha N. Oster
  • Semiconductor package having integrated stiffener region
    Patent number: 10923415
    Abstract: Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim, Shawna M. Liff, Feras Eid
  • THERMAL MANAGEMENT IN INTEGRATED CIRCUIT PACKAGES
    Publication number: 20210043573
    Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
  • BRIDGE FOR RADIO FREQUENCY (RF) MULTI-CHIP MODULES
    Publication number: 20210044030
    Abstract: Embodiments may relate to a radio frequency (RF) multi-chip module that includes a first RF die and a second RF die. The first and second RF dies may be coupled with a package substrate at an inactive side of the respective dies. A bridge may be coupled with an active side of the first and second RF dies die such that the first and second RF dies are communicatively coupled through the bridge, and such that the first and second RF dies are at least partially between the package substrate and the bridge. Other embodiments may be described or claimed.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Georgios Dogiamis, Telesphor Kamgaing, Johanna M. Swan
  • THERMAL MANAGEMENT IN INTEGRATED CIRCUIT PACKAGES
    Publication number: 20210043541
    Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
  • THERMAL MANAGEMENT IN INTEGRATED CIRCUIT PACKAGES
    Publication number: 20210043543
    Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
  • THERMAL MANAGEMENT IN INTEGRATED CIRCUIT PACKAGES
    Publication number: 20210043544
    Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
  • THERMAL MANAGEMENT IN INTEGRATED CIRCUIT PACKAGES
    Publication number: 20210041182
    Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
  • INTEGRATED FILTER STACK FOR A RADIO FREQUENCY (RF) FRONT-END MODULE (FEM)
    Publication number: 20210036685
    Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM) that includes a first acoustic wave resonator (AWR) die coupled with a package substrate. The RF FEM may also include a second AWR die coupled with the first AWR die. The first AWR die may be between the package substrate and the second AWR die. Other embodiments may be described or claimed.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Telesphor Kamgaing, Feras Eid, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
  • INTEGRATED RADIO FREQUENCY (RF) FRONT-END MODULE (FEM)
    Publication number: 20210036682
    Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM) that includes an acoustic wave resonator (AWR) die. The RF FEM may further include an active die coupled with the package substrate of the RF FEM. When the active die is coupled with the package substrate, the AWR die may be between the active die and the package substrate. Other embodiments may be described or claimed.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Telesphor Kamgaing, Aleksandar Aleksov, Feras Eid, Georgios Dogiamis, Johanna M. Swan
  • Piezoelectric package-integrated film bulk acoustic resonator devices
    Patent number: 10903818
    Abstract: Embodiments of the invention include a piezoelectric package integrated filtering device that includes a film stack. In one example, the film stack includes a first electrode, a piezoelectric material in contact with the first electrode, and a second electrode in contact with the piezoelectric material. The film stack is suspended with respect to a cavity of an organic substrate having organic material and the film stack generates an acoustic wave to be propagated across the film stack in response to an application of an electrical signal between the first and second electrodes.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Feras Eid, Adel A. Elsherbini, Telesphor Kamgaing, Georgios C. Dogiamis, Valluri R. Rao, Johanna M. Swan
  • Piezoelectric package-integrated contour mode filter devices
    Patent number: 10897238
    Abstract: Embodiments of the invention include a filtering device that includes a first electrode, a piezoelectric material in contact with the first electrode, and a second electrode in contact with the piezoelectric material. The piezoelectric filtering device expands and contracts laterally in a plane of an organic substrate in response to application of an electrical signal between the first and second electrodes.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Feras Eid, Georgios C. Dogiamis, Valluri R. Rao, Adel A. Elsherbini, Johanna M. Swan, Telesphor Kamgaing, Vijay K. Nair