Patents by Inventor Flynn Carson

Flynn Carson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170018507
    Abstract: A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die.
    Type: Application
    Filed: September 29, 2016
    Publication date: January 19, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Reza A. Pagaila, Flynn Carson, Seung Uk Yoon
  • Patent number: 9484279
    Abstract: A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: November 1, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Reza A. Pagaila, Flynn Carson, Seung Uk Yoon
  • Patent number: 9331007
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or LDA. A plurality of bumps is optionally formed over the semiconductor die. A bump is recessed within the opening of the encapsulant. A conductive ink is formed over the first surface of the encapsulant, bump and sidewall of the opening. The conductive ink can be applied by a printing process. An interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The interconnect structure is electrically connected to the semiconductor die. A semiconductor package is disposed over the first surface of the encapsulant with a plurality of bumps electrically connected to the conductive ink layer. The semiconductor package may contain a memory device.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: May 3, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Insang Yoon, Flynn Carson, Il Kwon Shim, SeongHun Mun
  • Patent number: 9236319
    Abstract: A stacked integrated circuit package system includes: providing a base integrated circuit package, and mounting a top integrated circuit package having a top interposer and a top encapsulation with a cavity therein or the cavity as a space between top intra-stack interconnects and the top interposer, with the top interposer exposed by the cavity, over the base integrated circuit package.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: January 12, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jong-Woo Ha, Flynn Carson, BumJoon Hong, SeongMin Lee
  • Patent number: 8723302
    Abstract: An integrated circuit package system includes: forming a base stacking package including: fabricating a base substrate, mounting an integrated circuit on the base substrate, positioning an input/output expansion substrate, having access ports around an inner array area, over the integrated circuit, and injecting a molding compound on the base substrate, the integrated circuit, and the input/output expansion substrate; and mounting a top package on the input/output expansion substrate.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: May 13, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Harry Chandra, Flynn Carson
  • Publication number: 20140103509
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or LDA. A plurality of bumps is optionally formed over the semiconductor die. A bump is recessed within the opening of the encapsulant. A conductive ink is formed over the first surface of the encapsulant, bump and sidewall of the opening. The conductive ink can be applied by a printing process. An interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The interconnect structure is electrically connected to the semiconductor die. A semiconductor package is disposed over the first surface of the encapsulant with a plurality of bumps electrically connected to the conductive ink layer. The semiconductor package may contain a memory device.
    Type: Application
    Filed: October 16, 2012
    Publication date: April 17, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Insang Yoon, Flynn Carson, Il Kwon Shim, SeongHun Mun
  • Patent number: 8598690
    Abstract: A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: December 3, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Harry Chandra, Flynn Carson
  • Patent number: 8409920
    Abstract: An integrated circuit package system and method of manufacture therefor includes: forming an area array substrate; mounting surface conductors on the area array substrate; forming a molded package body on the area array substrate and the surface conductors; providing a step in the molded package body; and exposing a surface conductor by the step.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: April 2, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Rajendra D. Pendse, Flynn Carson, Il Kwon Shim, Seng Guan Chow
  • Patent number: 8241965
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle; forming a pad extension having a spacing to the package paddle; forming a lead adjacent the pad extension, the pad extension between the package paddle and the lead; forming a conductive layer directly on and between the package paddle and the pad extension; and connecting an integrated circuit to the pad extension and the lead, the integrated circuit over the package paddle.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: August 14, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Flynn Carson, Zigmund Ramirez Camacho, Emmanuel Espiritu
  • Publication number: 20120119348
    Abstract: A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.
    Type: Application
    Filed: January 27, 2012
    Publication date: May 17, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Harry Chandra, Flynn Carson
  • Patent number: 8129832
    Abstract: A mountable integrated circuit package system includes: providing a carrier; mounting a first integrated circuit device over the carrier; mounting a substrate over the first integrated circuit device with the substrate having a conductor-free recess; connecting a first electrical interconnect under the conductor-free recess electrically connecting the carrier and the first integrated circuit device; and forming a package encapsulation over the carrier, the first integrated circuit device, the first electrical interconnect, the conductor-free recess, and partially exposing the substrate.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: March 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Flynn Carson, In Sang Yoon, SeongMin Lee, JoHyun Bae
  • Patent number: 8110441
    Abstract: A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: February 7, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Harry Chandra, Flynn Carson
  • Publication number: 20110306168
    Abstract: An integrated circuit package system and method of manufacture thereof includes: forming an area array substrate; mounting surface conductors on the area array substrate; and molding a molded package body, having a step surrounding a core section, on the area array substrate and the surface conductors, the step providing access to the surface conductors including providing a non-vertical slope from the core section to the step.
    Type: Application
    Filed: August 24, 2011
    Publication date: December 15, 2011
    Inventors: Rajendra D. Pendse, Flynn Carson, Il Kwon Shim, Seng Guan Chow
  • Publication number: 20110298101
    Abstract: A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 8, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Reza A. Pagaila, Flynn Carson, Seung Uk Yoon
  • Patent number: 8067268
    Abstract: A method for manufacturing of a stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer; and mounting a top integrated circuit package over the intermediate integrated circuit package.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Flynn Carson, Jong-Woo Ha, BumJoon Hong, SeongMin Lee
  • Patent number: 8030756
    Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: October 4, 2011
    Assignee: Chippac, Inc.
    Inventors: Taekeun Lee, Flynn Carson, Marcos Karnezos
  • Publication number: 20110079886
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle; forming a pad extension having a spacing to the package paddle; forming a lead adjacent the pad extension, the pad extension between the package paddle and the lead; forming a conductive layer directly on and between the package paddle and the pad extension; and connecting an integrated circuit to the pad extension and the lead, the integrated circuit over the package paddle.
    Type: Application
    Filed: August 18, 2010
    Publication date: April 7, 2011
    Inventors: Henry Descalzo Bathan, Flynn Carson, Zigmund Ramirez Camacho, Emmanuel Espiritu
  • Patent number: 7829382
    Abstract: A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: November 9, 2010
    Assignee: Chippac, Inc.
    Inventors: Marcos Karnezos, Flynn Carson, Youngcheol Kim
  • Publication number: 20100224979
    Abstract: A method for manufacturing of a stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer; and mounting a top integrated circuit package over the intermediate integrated circuit package.
    Type: Application
    Filed: May 19, 2010
    Publication date: September 9, 2010
    Inventors: Flynn Carson, Jong-Woo Ha, BumJoon Hong, SeongMin Lee
  • Patent number: 7750454
    Abstract: A stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer, and mounting a top integrated circuit package over the intermediate integrated circuit package.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: July 6, 2010
    Assignee: STATS ChipPAC Ltd.
    Inventors: Flynn Carson, Jong-Woo Ha, BumJoon Hong, SeongMin Lee