Patents by Inventor François Tailliet

François Tailliet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reconfigurable sense amplifier for a memory device
    Patent number: 9761316
    Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: September 12, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Victorien Brecte
  • Communication on an I2C bus
    Patent number: 9753886
    Abstract: A communication system includes an I2C bus interconnecting at least one first device and one second device. At least one direct data link, other than the I2C bus, interconnects the first and second devices. The system is configurable to operate in: a first operating mode providing for data only transmission between the first and second devices over the I2C bus; and a second operating mode providing for simultaneous data transmission between the first and second devices over both the I2C bus and said data link.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: September 5, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francois Tailliet
  • Non-volatile memory device having a memory size
    Patent number: 9753665
    Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 5, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • Apparatus and method for EEPROM select transistor breakdown voltage management
    Patent number: 9747053
    Abstract: A memory device of the non-volatile electrically-erasable and programmable memory type is provided. The memory device includes a matrix memory plane of memory cells connected to bit lines. Programming circuitry is configured to select a memory cell and to apply a programming pulse to the corresponding bit line. The memory plane is disposed in a local well at a floating potential and the programming circuitry is configured to increase the potential of the local well simultaneously with the application of the programming pulse to the bit line of a selected memory cell.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: August 29, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: François Tailliet
  • Apparatus and Method for EEPROM Select Transistor Breakdown Voltage Management
    Publication number: 20170242608
    Abstract: A memory device of the non-volatile electrically-erasable and programmable memory type is provided. The memory device includes a matrix memory plane of memory cells connected to bit lines. Programming circuitry is configured to select a memory cell and to apply a programming pulse to the corresponding bit line. The memory plane is disposed in a local well at a floating potential and the programming circuitry is configured to increase the potential of the local well simultaneously with the application of the programming pulse to the bit line of a selected memory cell.
    Type: Application
    Filed: July 27, 2016
    Publication date: August 24, 2017
    Inventor: FRANÇOIS TAILLIET
  • Method for Writing in an EEPROM Memory and Corresponding Device
    Publication number: 20170243648
    Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.
    Type: Application
    Filed: July 27, 2016
    Publication date: August 24, 2017
    Inventor: François Tailliet
  • Semiconductor structure and memory device including the structure
    Patent number: 9728248
    Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: August 8, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • SINGLE-WIRE BUS COMMUNICATION PROTOCOL
    Publication number: 20170206182
    Abstract: A method to transmit data over a single-wire bus wherein a first communication channel is defined by pulses of different durations according to the state of the transmitted bit and depending on a reference duration, and a second communication channel is defined by the reference duration.
    Type: Application
    Filed: February 2, 2017
    Publication date: July 20, 2017
    Inventors: Gilles Bas, Hervé Chalopin, François Tailliet
  • Method for writing into and reading a multi-levels EEPROM and corresponding memory device
    Patent number: 9711230
    Abstract: During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is controlled by the level of the control voltage applied to the control gate and the item of data is de facto written with the numerical value during the putting into conduction of the cell. The programming is then stopped.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: July 18, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Reconfigurable Sense Amplifier for a Memory Device
    Publication number: 20170154683
    Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
    Type: Application
    Filed: April 28, 2016
    Publication date: June 1, 2017
    Inventors: François Tailliet, Victorien Brecte
  • Method for Reading an EEPROM and Corresponding Device
    Publication number: 20170125112
    Abstract: One embodiment provides a method for reading a memory cell of a memory plane of a memory of the erasable electrically-programmable ROM type. The word line and of the bit line to which the memory cell belongs are selected and the content of the cell is read via a read amplifier. One input of the read amplifier is connected to the bit line and pre-charged at a pre-charge voltage. During the read operation, a source voltage higher than the pre-charge voltage is applied to the source of the floating-gate transistor of the cell. A read current flows from the cell towards the input of the read amplifier and then flows through a programmed cell.
    Type: Application
    Filed: June 15, 2016
    Publication date: May 4, 2017
    Inventors: François Tailliet, Marc Battista, Victorien Brecte
  • Single wire bus communication protocol
    Patent number: 9639500
    Abstract: A method for transmitting data over a single-wire bus wherein a first communication channel is defined by pulses of different durations according to the state of the transmitted bit and depending on a reference duration, and a second communication channel is defined by the reference duration.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: May 2, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Gilles Bas, Hervé Chalopin, François Tailliet
  • Non-Volatile Memory Device Having a Memory Size
    Publication number: 20170090813
    Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.
    Type: Application
    Filed: February 25, 2016
    Publication date: March 30, 2017
    Inventors: François Tailliet, Marc Battista
  • Method for Managing the Write Cycle of an EEPROM
    Publication number: 20170092357
    Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.
    Type: Application
    Filed: February 25, 2016
    Publication date: March 30, 2017
    Inventors: François Tailliet, Marc Battista
  • Compact memory device of the EEPROM type with a vertical select transistor
    Patent number: 9583193
    Abstract: Integrated non-volatile memory device includes an integrated memory cell of the EEPROM type with a floating-gate transistor and a selection transistor connected in series between a source line and a bit line, and a programming circuit for the memory cell. The selection transistor is connected between the floating-gate transistor and the source line. The programming circuit is configured for programming the at least one memory cell with a programming voltage split between a positive voltage and a negative voltage.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 28, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Method and system for managing a writing cycle of a data in a EEPROM memory cell
    Patent number: 9576670
    Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: February 21, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • Method for Writing in an EEPROM Memory and Corresponding Memory
    Publication number: 20170039001
    Abstract: According to one mode of implementation it is proposed to automatically accelerate the write operation by deleting on the basis of the values of the data to be written and optionally on the basis of the values of the data present in the memory the erasure step or the programming step, so doing while optionally using a conventional write command. When the memory is equipped with an error-correcting code based on a Hamming code, a property of the latter makes it possible readily to implement this possible acceleration of the cycles of writings within the memory. This property is that according to which when all the bits of the bytes of a digital word grouping together n bytes are equal to zero, the check bits associated with these bytes are also all equal to zero.
    Type: Application
    Filed: February 27, 2016
    Publication date: February 9, 2017
    Inventors: François Tailliet, Marc Battista
  • Method and System for Managing a Writing Cycle of a Data in a EEPROM Memory Cell
    Publication number: 20170040060
    Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.
    Type: Application
    Filed: August 23, 2016
    Publication date: February 9, 2017
    Inventors: François Tailliet, Marc Battista
  • Electronic device with a radiofrequency function
    Patent number: 9544025
    Abstract: An electronic device includes at least one processing circuit connected through at least one terminal at a first reference voltage. At least one radio frequency communication circuit is connected at least to receive the reference voltage. At least one first pad is intended to be taken to a second reference voltage of at least one electronic circuit external to the device. At least one first resistive impedance is coupled between the terminal and the first pad.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: January 10, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • EEPROM architecture wherein each bit is formed by two serially connected cells
    Patent number: 9514820
    Abstract: An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line. Each memory cell is formed by: a first select transistor with a first source-drain path; a second select transistor with a second source-drain path; a first floating gate transistor with a third source-drain path; and a second floating gate transistor with a fourth source-drain path. The first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line. The word line for each row of the memory is coupled to the gate terminals of the first and second select transistors. The control gate line for each row in coupled to the gate terminals of the first and second floating gate transistors.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: December 6, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francois Tailliet